VHDL实现任意大小矩阵加法运算

本设计是VHDL实现任意大小矩阵加法运算
通过加法实现两个矩阵相加，得到的结果存储在Buffer中

使用VHDL语言
在vivado上进行综合和仿真

设计代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values

– Uncomment the following library declaration if instantiating
– any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity IntMatAddCore is
port(
Reset, Clock, WriteEnable, BufferSel: in std_logic;
WriteAddress: in std_logic_vector (9 downto 0);
WriteData: in std_logic_vector (31 downto 0);-- input two matrix 可输入任意大小矩阵
WriteDataB: in std_logic_vector (31 downto 0); – input two matrix 可输入任意大小矩阵
ReadAddress: in std_logic_vector (9 downto 0);
ReadEnab