[common error] the DDR type of FPGA device is selected incorrectly

ZedBoard Common development errors ：

DDR The model configuration of is wrong . The indirect result is , In the debug debug when , Will find cpu Always in running The state of , But you can't see the printed information on the console , And whether it's just PS End or PS、PL Both ends are used , No printing information can appear on the console , But the program can be burned on the board （program FPGA I found that the blue light on the board will be on ）, This shows that the board itself is ok , The problem of wiring is eliminated , The final discovery is to configure block design Of DDR Information time ,DDR The reason for choosing the wrong model , Wrong model selection will lead to , After the program is burned into the board , But because there is no configuration for memory , Therefore, the program cannot be saved , Therefore, it is impossible to output information through the serial port ,cpu Will be in a constant running The state of .DDR The relevant configuration information of can be found in zedboard Of user guide（ug） It's on the Internet .