How vivado adds timing constraints

One FPGA In addition to pin assignment , There is also an important constraint , That's the temporal constraint , Here through to
The derivation method demonstrates that if a timing constraint

1. Click on “Run Synthesis” Start to synthesize
   
2. Pop up the dialog box and click “OK”
   
3. After synthesis, click “Cancel”

4) Click on “Constraints Wizard”

5) Click... In the pop-up window “Next”

6) The timing constraint wizard analyzes the clock in the design , Here is the “sys_clk” The frequency is set to 50Mhz, And then click
“Skip to Finish” End the timing constraint wizard .

7) Click... In the pop-up window “OK”
8) Click on “Finish”
9) This is the time top.xdc The file has been updated , Click on “Reload” Reload file , And save the file

set_property PACKAGE_PIN U18 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]


set_property PACKAGE_PIN J16 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]


# Timing constraints 
create_clock -period 20.000 -name sys_clk -waveform {
    0.000 10.000} [get_ports sys_clk]