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SPI master rx time out中断
2022-07-07 13:29:00 【lixingdian】
背景:测试spi的time out中断,板子A master rx,板子B slave tx。master设置成超时中断TIME OUT。
slave发数据过来,master并没有触发超时中断。图像上很准确,开始担心是板子这个功能有问题,但是模拟的没问题。应该是设置问题。
模拟告诉我,清除fifo会清除time out寄存器。于是我在初始化的时候清除一次,后面就不会清除flfo。但实际上这样波形都不正确了,究竟是slave怎么把数据发给master。而且依旧触发不了中断,如果设置成done中断就可以触发。但就不是我们想要的time out中断了。模拟又告诉我说rx trigger level为空,设置数据会触发,设置后也无效,后来发现该位有数值限制,不能过大,过大会变成0。设置成正确的数字也无法触发中断。模拟又告诉我,传输数据时因为要接收的数据挺多的,cs一直拉低,会导致板子认为还在接收数据,会触发rxready中断,而不是time out中断。之所以要接收的数据挺多,是因为我的master设置SPI_DataLen为512(bits)了。在文档中解释:
Tx/Rx length
Spi在传输时,有效的SCK数
也间接的反映了发送或者接收数据的长度。
所以当我设置datalen为8以后,就可以触发正常的TIME OUT中断了。
后来看time out中断的文档,才发现自己文档读的不够详细。其实作者写的很清晰了。
当一次传输结束以后,rx fifo中有数据,但是数据量不够触发rx trigger level时,超过一定时间,就会触发time out寄存器。如果清除了fifo肯定也会清除掉调time out计数器。
所以要测试time out,需要
1、发数据的间隔时长长,长到接收完数据后足够触发完TIME OUT再清除fifo。
2、数据量小于rx trigger level,并且不会过多触发rx ready中断。
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