Topic collection of FIFO minimum depth calculation

asynchronous FIFO Depth calculation

One 、 Writing clocks is faster than reading clocks

1、

 Time of data transmission  = FIFO Fill in the time 
FIFO Fill in the time  = FIFO depth  / （ Write rate  -  Readout rate ）
 Data transfer time  =  Data volume  /  Write rate 
 therefore  
FIFO depth  / （ Write rate  -  Readout rate ） =  Data volume  /  Write rate 

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2、 depth = The amount of data written （ Burst length ） - Read data volume （ How much data have you read in the same time ）

 We need to write clock and write data according to , Get burst length , Then figure out how long the data needs to be written , In the time of writing data , How much data does the reading clock read .

3、 The worst （ Back to back ）

fifo_depth = burst_length - burst_length * X/Y * r_clk/w_clk
XY Express : Every time Y The clock period has X Data readout FIFO

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Two 、 Writing clock is slower than reading clock
1、 Writing clock is slower than reading clock , And there is no idle cycle in the process of reading and writing

 In this case, data loss will never happen ;fifo The depth of this is 1 that will do .

2、 Writing clock is slower than reading clock , And there is an idle period during the reading and writing process

 depth  =  The amount of data written （ Burst length ） -  Read data volume （ How much data have you read in the same time ）

Sync FIFO Depth calculation

3、 ... and 、 Read and write clocks are consistent
1、 The read-write clock frequency is the same , But there are idle cycles in the process of reading and writing .

 depth  =  The amount of data written （ Burst length ） -  Read data volume （ How much data have you read in the same time ）

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Look at the topic

subject 1：
Now we need to pass A Write 10 All the data , And send it to by reading the clock B, Write clock 50Mhz, Read the clock as 40mhz, If you want data not to be lost , So you need to AB Insert between FIFO, So how deep do we need to insert FIFO Well ？

FIFO depth  / （ Write rate  -  Readout rate ） =  Data volume  /  Write rate 

Problem solving ：

FIFO depth / （ 50 Mhz- 40Mhz ） = 10 ten thousand / 50Mhz , be 10 ten thousand / 50MHZ = 1 / 50 s = 0.002s = 2ms
.
2 ms = FIFO depth / （ 50 Mhz- 40Mhz ）, Then depth = 2ms / 100ns = 20000 = 20k
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therefore FIFO Depth is 20 k .

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subject 2：
It is known that ： clock frequency ：clkA = clkB / 4 ; Clock cycle ： clk (en_B) = clkA * 100 ;en_B Duty ratio 25%. seek FIFO depth .

Explain ：

hypothesis clkA = 100 MHz ,clkB = 400Mhz, be TclkA = 10ns,TclkB = 2.5ns,en_B The period of is clkA Of 100 times , therefore Ten_B = 1000ns because enB Duty ratio 25%, Therefore, the high level of the signal continues 250ns.
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Generally speaking, writing is faster than reading , So suppose clkA To read the clock ,clkB Write clock for , When enB High voltage usually , Write clock write data , Amount of data written = 250ns / 2.5ns =
100 Data .
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When write enable is effective , With data , Therefore, read operation can be performed , Reading data = 250ns / 10ns = 25 Data
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depth = Write data - Read the data = 75

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subject 3：—— Sync FIFO

For synchronization fifo, Every time 100 individual cycle Can write 80 Data , Every time 10 individual cycle You can read 8 Data ,fifo At least the depth of ？

Problem solving ：
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Every time 100 individual cycle Can write 80 Data , In order to get safer FIFO depth , We need to think about the worst , In case of data loss , Back to back mode , empty 20 A clock , be left over 80 A clock writes 80 Data , Reuse 80 A clock writes 80 Data , empty 20 A clock , The result is to write in succession 160 Data , Sharing the 200 A clock , The burst length is 160
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To paraphrase formula ,fifo_depth = burst_length - burst_length * X / Y * r_clk/w_clk
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Because it's synchronization FIFO, The reading and writing clocks are the same , be r_clk=w_clk; fifo_depth = 160 - 160 *8 / 10 * 1 = 160-128 =32 , Depth is 32

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subject 4：—— asynchronous FIFO
wclk＝200mhz,100 individual wclk Write in 40 Data ,rclk＝100mhz,10 individual rclk Read in 8 Data . that fifo Depth is ？

How to solve the problem 1：
We still consider the worst case , Back to back , Empty space 60 individual wclk, be left over 40 individual wclk I have 40 Data , next 40 individual wclk Write 40 Data , empty 60 individual wclk, Then the number of burst data is 40+40=80, It was used 200 individual wclk.
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The formula ：fifo_depth = burst_length - burst_length * X / Y * r_clk/w_clk
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Then depth = 80 - 80 * 8 / 10 * 1/2 = 48 .
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Be careful ： because FIFO The depth of the is generally 2 Omega to an integer power , Conform to the code conversion rules of qualified lightning codes , For the calculated depth 48, Choose a bigger one 2 To an integer power of , such as 64.

How to solve the problem 2 ：

The formula ： depth = The amount of data written （ Burst length ） - Read data volume （ How much data have you read in the same time ）
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wclk＝200mhz = 1000 / 200mhz = 5ns, Burst length 80, Then write the time ：5ns * 80 = 400 ns
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rclk＝100mhz = 1000 / 100mhz = 10ns, Every time 10rdclk read 8 Data ,10rdclk =100ns, therefore 100ns read 8 Data , stay 400ns in , Reading data = 4 * 32 .
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depth = The amount of data written - Read data volume = 80 - 32= 48

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subject 5：—— Write clock Than Slow clock fast , There is no idle cycle in the read / write project （ In a burst , Reading and writing are carried out continuously under respective clocks ）

wclk = 80Mhz ,rclk = 50mhz, Burst length 120, There are no idle cycles in the process of writing and reading .

Problem solving ：

wclk = 80Mhz = 1000 / 80mhz = 12.5 ns
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Write time = 12.5 ns * 120 = 1500
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At the same time , Calculate how much data to read . rclk = 50mhz = 20ns. Reading data = 1500 /20 = 75 data
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Therefore depth = Writing data - Reading data = 120 - 75 = 45

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subject 6：—— Write clock Than Slow clock fast , And there are idle cycles in the read / write project

wclk = 80Mhz ,rclk = 50mhz, Burst length 120, Two write clocks write one data ,4 Read one data in one read clock cycle .

Problem solving ：

wclk = 80Mhz = 1000 / 80mhz = 12.5 ns
.
Write the number of data 120, Every two wclk Write a data , Then every 25ns Write a data . Write time = 120 * 25 = 3000ns
3000ns Inside , Ask how much data you can read .
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rclk = 50mhz = 20ns, Every time 4 individual rclk Read a data , So every 80ns Read a data .3000ns Readable data = 37.5 Data = 37 Data .
depth =120 - 37 = 83

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subject 7：—— The write clock is slower than the read clock , And there is no idle cycle in the process of reading and writing

wclk = 30Mhz ,rclk = 50mhz, Burst length 120.

In this case, data loss will never happen ;fifo The depth of this is 1 that will do .

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subject 8：—— The write clock is slower than the read clock , And there is an idle period during the reading and writing process
wclk = 30Mhz ,rclk = 50mhz, Burst length 120, Every two wclk Write a data , Every time 4rclk Read a data .

Problem solving ：

wclk = 80Mhz = 1000 / 30mhz = 100/3ns
.
Write the number of data 120, Every two wclk Write a data , Then every （100/3ns）* 2 Write a data .
Write time = 120 * （100/3ns）* 2 = 8000ns
8000ns Inside , Ask how much data you can read .
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rclk = 50mhz = 20ns, Every time 4 individual rclk Read a data , So every 80ns Read a data .8000ns Readable data = 100 Data
depth =120 - 100 = 20

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subject 8：—— The read-write clock frequency is the same , But there are idle cycles in the process of reading and writing .
wclk = 50Mhz ,rclk = 50mhz, Burst length 120, Every two wclk Write a data , Every time 4rclk Read a data .
Problem solving ：

wclk = 50Mhz = 1000 / 50mhz = 20ns
.
Write the number of data 120, Every two wclk Write a data , Then every （20ns）* 2 Write a data .
Write time = 120 * 40ns = 4800ns
4800ns Inside , Ask how much data you can read .
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rclk =wclk, Every time 4 individual rclk Read a data , So every 80ns Read a data .4800ns Readable data = 60 Data
depth =120 - 60 = 60

FIFO Knowledge mastery
FIFO Only valid in case of data burst ; No continuous data input and output , If there is a continuous data flow , Then what is needed FIFO The size of should be infinite .

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