4. PCIe interface timing

In the previous article, I briefly introduced the IPcore interface.In general, the interface is as shown below

Data is received and sent through transmit TLP interface and Receive TLP interface.The timing of sending and receiving data only describes the relationship between these interfaces.Take the interface timing of PCIe x1 from the manual

Data sending

The picture above is the x4 interface. The 5G IP we use, the timing is similar to this, but the tx_val will be valid at intervals.The above timing

Before EP sends data, first send tx_req_vc0 high, indicating request to send, wait for tx_rdy_vc0 to be high to start sending, when tx_rdy_vc0 is high, place data on yx_data_vc0 on the rising edge of the next clock, and pull high tx_st_vc0 signal. tx_rdy_vc0 remains high until the last data of the TLP packet, so this tx_rdy_vc0 signal can be used as a read enable signal for non-pipeline fifo.

tx_end_vc0, indicating that the data line is the last data of TLP.

tx_ca_*h_vc0 and tx_ca_*d_vc0 must be checked before each request is sent, and the corresponding value will be decremented by one after the transmission is completed. These two types of flags indicate whether the upper port has resources to forward your sent data

The above picture is the timing of sending two data

The sending timing of the above picture is only the header, there is no data corresponding to tx_ca_*d_vc0 and there is no change

The last data sent in the above picture is not enough 64bit, at this time the dwen signal indicates that 63:32bit is valid

Burst mode, send two TLP packets, the req signal remains valid until the last TLP packet sends the rdy signal

Void the TLP packet, pull the tx_nlfy signal high at any time, void this TLP packet, no need to send the tx_end signal again

When the x4 in the above figure is downgraded to x1, the sequence diagram is the same as above. The x1 used in our project is the same as above.In this figure, when tx_val is high, the signal changes

Data reception

When a TLP data packet is sent, rx_st_vc0 will be pulled high, at this time the first data will appear on the data line, one data per clock, when rx_end_vc0 is high, it means that the data line islast data.If there is an ECRC error, rx_ecrc_err_vc0 will be pulled high at the last data moment; if there is a problem with the length of the TLP, rx_malf_tlp_vc0 will be pulled high

tlp receive data

Receive ECRC error

There is a problem with the TLP length