Simulation scheduling problem of SystemVerilog (1)

Although now SystemVerilog Occupy the mainstream position in simulation verification , But take a look Verilog How to simulate , To learn later systemverilog The simulation feature of is also helpful . This article mainly studies verilog Some simulation features of , Because on the one hand , If it's written RTL The code quality is not high , So different simulators / When the tool is simulating , Yes verilog The explanation may be different , The simulation results are different ; On the other hand , Because in Verilog HDL Linguistic IEEE In the standard , Its semantics adopts a non formal description method , Therefore, simulation tools from different manufacturers 、 There must be differences in the background strategy of comprehensive statements , The same paragraph RTL Code , The running results of different simulation software may be different . So we should first understand verilog Simulation features of , Avoid writing Make the simulator produce ambiguous results Code .

1.0  Simulation time （ Current simulation time and future simulation time ）

　① Simulation time ： Means by Emulator simulator To maintain the time value , It is used to simulate the circuit used Real time modeling .（ explain ： We know , In a simulation case in , By imposing specific incentives sequence, Then you can see the hardware circuit pair stimulus There was a reaction , The output of hardware circuit changes , This change can be monitor perhaps scoreboard Acquired . The whole process of hardware circuit also takes time t Consumption to produce output . be simultor The real time behavior of the simulated hardware circuit , Modeling .）

　②0 Time is the starting time of simulation ： When the simulation time advances to At some point in time when , The Point in time This is called Current simulation time , And any time after that is called Future simulation time .

Be careful ： Simulation time is just a time mark of circuit behavior , And simulation program in PC Running time on the machine It doesn't matter. . For a very complex program , Although only Very short simulation time , Also needed The simulator runs Longer Time ; For simple programs , Real time simulation takes a long time , It only needs a short running time . The following figure , The top column is marked with “ns” The number in is Simulation time . Essentially , Simulation time has no unit , The reason why the figure appears “**ns”, It's because `timescale The definition of the statement leads to .

·`timescale Used to define the unit of delay and the precision of delay , Such as `timescale  1ns/100ps Then the unit of time is 1ns, The precision is 100ps.· Time unit , Represents the unit of measurement during simulation , Such as delay 1,1ns; Accuracy indicates the range that the simulator only recognizes , For example, the accuracy is 100ps, So if you 1.3ns, The compiler recognizes , But if you write 1.32, Then because the accuracy can't reach that fine , therefore 0.02 Be rounded off .·`timescale It affects all modules , Know when you meet someone else `timescale.

2.0  Event driven simulation features  

Verilog It has event driven simulation characteristics . Let's first understand what is event （ It can be understood from the following three aspects ）：

①Verilog It can define events (event), It can be done to testbench The signal inside is monitored , If the event triggering conditions are met, the event will be triggered and the corresponding processing will be triggered ,Verilog Inside event For simulation purposes only , Can't synthesize .② for example , Designers can define “ Output changes ” perhaps “ Input change ” For an event , Such as edge sensitive events 、 Level sensitive events .③ Block assignment 、 Nonblocking assignment 、 Some system functions can also be events .

Verilog A certain behavior in can be regarded as an event , and verilog Simulation time , It is driven by certain events . For example, it may not be very appropriate ：

· Xueba gives himself a day's life planning yes ： Get up in the morning, have breakfast and then go to class , We will have a rest in the dormitory at noon and go to class in the afternoon , In the evening, go to the library carefully and then go back to bed to have a rest .

·（ In a day , Give a person a kind of ： What Xueba did   Drive learning time Down The feeling of flow , That is, Xueba works to drive Xueba to live constantly ;emmm It seems to give people a feeling that I think so I am ...）

· Learn to dominate a day's life Compared to the simulation process , A certain behavior of Xueba （ For example, eat breakfast ） like verilog An act of / event （ Such as assignment ）, Xueba's Day is driven by these behaviors , Like verilog It's event driven （ Such as ：assign Assignment events are driving you verilog The simulation of ,always It also drives your simulation and so on ）, Speaking of this , You should know verilog Events What is it

Note appended ： Another simple understanding is , An event is a change in one signal that causes a change in another signal , If there is no change in other signals , It is not called an event .

Be careful ： If there is no event driven , Control simulation time will not advance , But not all events can drive simulation time , Simulation time can only be advanced by one of the following events ：

　　· Defined gate level or wire Transmission delay ;

　　· Update Events （ Finger net 、 Any change in register value , As mentioned above, the input and output changes ）;

　　·“#” Event control ;

　　·“always” Keyword introduced event control ;

　　·“wait” Waiting statement

All simulation events are advanced in strict accordance with the simulation time , That is to say, perform the right operation at the right time , in fact , The above events are cycles 、 Trigger each other , To jointly promote the progress of simulation time . If there are multiple events to be executed at the same simulation time , First of all, it needs to be based on the relationship between them priority To determine who executes first . If the priority is the same , The execution mode of different simulators is different , It may be random , May also be Execute in the order the code appears . Most simulators use the latter method . You should know here Verilog What's the matter with event driven simulation .

Two 、Verilog Hierarchical event queue and (VCS) How the simulator works

　　 Did you learn verilog We should all know （ At least I've heard of it ）verilog It has the meaning of concurrency （ Such as assign、always Statements are parallel ）, In the simulation ,Verilog HDL The sentence is also Serial execution Of , Its hardware oriented Parallel features Through its linguistic meaning / Semantics to achieve . in other words , Although in the simulation, all the code is executed serially , But due to the existence of grammar and semantics , The parallel meaning and characteristics of the code will not be lost .

that verilog How to use serial in the simulator   To embody   The meaning of parallelism   What about ？

　　 answer ： you verilog There are various events ？ I'll use the simulator to verilog Events are layered （ namely Verilog Hierarchical event queue ）, Then layered , Perform... Layer by layer . To be specific ：Verilog have Discrete event time simulator Characteristics of , in other words At discrete points in time , beforehand Arrange all events , And put them according to Time sequence into the event waiting queue . The first event At the top of the waiting queue , The later events are placed next . The simulator is always Current simulation time Move The whole event queue , And start the corresponding process . In the process of running , It is possible to generate more events for subsequent processes and place them in the appropriate position in the queue . Only At the current moment, after all events are running , The simulator advances the simulation time , Run the next event at the top of the event queue .

　　 among , Active events have the highest priority （ The first to perform ）, The priority of monitoring events is the lowest , And the execution order of each event in the active event is random （ notes ： For convenience , In a general simulator , Different events in the same area are executed according to the scheduling order , That is, which event code is in front , Just execute which event first ）. The simulator first follows Simulation time Sort Events , Then sort the events in the current simulation time according to the priority order . Active events have the highest priority Events , Inactive Events The priority level of , Nonblocking assignment The priority of is the third , Monitoring events Is the fourth priority ; Future events Has the lowest priority . All events in the future simulation time will be temporarily stored in the future event queue , When the simulation process advances to a certain moment , At this time, all events will be added to the current simulation event queue . stay Verilog in , Event queues can be divided into 5 Different areas , Different events are placed in different areas according to regulations , The order of execution depends on the priority , The following figure lists some Verilog Hierarchical event queue :

As can be seen from the above figure , Blocking assignment is an active event , Will execute immediately , This is it. Block assignment “ Calculation completed , Update now ” Why . Besides , Because in the hierarchical event queue , Only the top events in the active events are called out , And after execution , To execute the following events .

The simulation process model is as follows ：　　　　　

　　　　　　　　

Use the specific flow chart as shown below ：

stay systemverilog in , It enriches and perfects the concept of simulation scheduling . Learning simulation scheduling problem , In order to ensure that the verification environment drives and samples the hardware signals accurately .

Start Simulation is ：

A： It will at the same time Read all Of initial、 always、assign Wait for these statement blocks , Then wait for the first event to happen （ For example, a rising edge ）, Get into

B： After reading in ,(VCS) The simulator will follow these statements A fixed order Write it into a queue （ such as always in begin...end Block statement , The statements in the block will be in accordance with The original order write in ）, Then execute the statement without delay （ Such as no # Time delay of 、 Initialized variable expression, etc ）. When a part of the statement is executed , That is, after executing the statement without delay , Get into

C: Simulator handle At present Time Set as 0, That is to say, the simulation of the running time of the circuit has really begun , This is the real starting point of the circuit . After setting up , Get into

D（ Then there is the layered simulation sequence ）: The simulator enters a active Region , In this area , The simulator mainly executes some primitives （ Such as UDP）、display System function 、 No delay assign、 Block assignment （ One step in place ）、 Nonblocking assignment （ Only perform the calculation on the right , Assignment incomplete ）. Then enter

E:inactive District , if there be # Time delay of , This area handles some delays . Then enter

F: Non blocking assignment area , This area performs non blocking assignment . Then enter

G：monitor District , That is, the area where the monitoring system functions are executed , Such as implementation $monitor Series of functions .（ This makes monitoring statements have different usages , For example, when monitoring non blocking assignment , Do you use display Because in active District , Therefore, only the old value can be monitored , Because the non blocking assignment has not been completely completed monitor You can detect New value after non blocking assignment ） Last Get into

H:future District , Handle some other commands and code .

　　 I learned these first today , It's better to understand these contents , If you can remember , That's the best （ If you can't remember it, turn it over several times and remember it ）. Next plan to start learning VCS 了 .