Collation and review of knowledge points of Microcomputer Principle and interface technology - pure manual

Hello everyone , I meet you again , I'm your friend, Quan Jun .

Tomorrow is the exam , A wave of knowledge points sorting . All right , You can't come to me for the final exam ！

Chapter one

1. Sort by microprocessor bytes

 4  Bit microprocessor 
 8  Bit microprocessor 
 16 Bit microprocessor  
 32 Bit microprocessor 

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2. This must be memorized , Either short answer or short answer , There must be a brief answer

3. Systems software

 Give an example to judge whether it is system software ！
 Common system software ：
 operating system 、 Programming language design 、 Language handler 、 Database management program 、 System auxiliary handler 

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Chapter two

1. Performance index of microprocessor

a. The word is long  CPU Number of data bits that can be processed at the same time  
b. Main frequency  CPU The clock frequency of , The higher the dominant frequency , The faster the computation is 

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2.8086 Programming structure ( master ) This must be memorized , Short answer questions will come out

 Functionally 8086 In two parts , Bus interface part (BIU)  and   Executive parts (EU)
a.	 Bus interface unit 
	a)	4 individual 16 Bit segment address register 
		i.	CS  Code segment address register 
		ii.	DS  Segment address register 
		iii.	ES  Additional segment address register 
		iv.	SS  Stack segment address register 
	b)	16 Bit instruction pointer register  IP
	c)	20 Bit address adder 
	d)	6 Byte instruction queue buffer 
b.	 Executive parts 
	a)	4 General registers  AX、BX、CX、DX
	b)	4 Special registers 
		i.	 Cardinal pointer register  BP
		ii.	 Stack pointer register  SP
		iii.	 Source index register  SI
		iv.	 Destination address register  DI
	c)	 Flag register  FR
	d)	 Arithmetic logic unit ALU ( Arithmetic and logic operations )

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3.8086 The flag registers of are 16 position ,7 Bit unused ,,, Just know when it means what

a.	 Status identification 6 individual 
	a)	 sign indicator  SF
	b)	 Zero mark  ZF
	c)	 Parity mark  PF
	d)	 Carry mark  CF
	e)	 Auxiliary carry flag  AF
	f)	 Overflow sign  OF
b.	 Control signs 3 individual 
	a)	 Direction signs  DF
	b)	 Interrupt allow flag  IF
	c)	 Tracking signs  TF 
 There are symbols and meanings ：ZF  SF  PF  OF
 Unsigned makes sense ：PF  ZF  CF  AF

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4.8086 Bus cycle – Fill in the blanks and choose

 from 4 Clock cycles make up , The clock period is CPU The most basic unit of time measurement 
4 A clock cycle is called 4 Status ：T1、T2、T3、T4
Tw Put it in T3 and T4 Between 

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5.8086 Minimum mode typical configuration （ Master the quantity 、 name 、 Chip model 、 function ）( master ) You don't recite this , The teacher will not let you go , Short answer questions must be either the largest or the smallest

a. Yes 1 slice 8284A, As a clock generator , Provide clock signal and synchronization ready Signals and reset The signal 
b. Yes 3 slice 8282 or 74LS273, Used as an address latch , Temporary storage address 
c. Yes 2 slice 8286/8287, As a bus transceiver , Increase the driving capacity of the data bus 
d. Yes 1 slice 8086, As a microprocessor , be responsible for CPU For memory and IO Port data transmission and instruction execution 

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6.8086 Maximum mode typical configuration of ( master ) The requirements are the same as the minimum mode

a.	 There are two or more 8086, As a microprocessor , The function is the same as the minimum mode 
b.	 Yes 1 slice 8284A, As a clock generator , The function is the same as the minimum mode 
c.	 Yes 3 slice 8282 or 74Ls273, Used as address latch , The function is the same as the minimum mode 
d.	 Yes 2 slice 8286/8287, As a bus transceiver , The function is the same as the minimum mode 
e.	 Yes 1 slice 8288, As a bus controller , Whether the control bus gives way 
f.	 Yes 1 slice 8259A, As an interrupt controller , Controls whether interrupts are handled 

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7. interrupt – Fill in the blanks and choose

a.	 Break classification ：
	a)	 Hardware interrupt / External interrupt 
		i.	 Unshielded interrupt  –  Pin NMI
		ii.	 Maskable interrupt  –  Pin INIR
	b)	 Software interrupt / Internal interruption 
b.	 Interrupt vector and interrupt vector table 
	a)	 The interrupt vector table can hold at most 256 Interrupt vectors 
	b)	 An interrupt vector accounts for 4 Storage unit 
	c)	 When looking up the vector table , Interrupt type number *4 Is the starting address , continuity 4 Storage unit 

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8. Interrupt response process Fill in the blanks and choose

INAT The pin is valid twice , The first valid is the interrupt request signal , The second valid is the transmission interrupt type number 

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9. Memory Mainly fill in the blank , Master the addressing method

a.	 Physical address  =  Segment address  * 16 +  Logical address 
b.	I/O Two methods of addressing ： 
	a)	 Memory image 
	b)	I/O Port independent addressing 

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The third chapter

1.Pentium The addressing mode of ( master ) You must fill in the blanks , Give you instructions and ask how , Just read the title description clearly

a.	 Immediate addressing 
	a)	 An immediate can only be used as a source operand , Cannot be used as destination operand 
b.	 Register addressing 
c.	 Input / Output port addressing 
	a)	I/O Direct addressing 
	b)	I/O Indirect addressing 
d.	 Memory addressing 
	 Valid address EA =  Base address  +  Address  *  The scaling factor  +  Displacement 
	a)	 Direct addressing                           MOV AX , [1070H]
	b)	 Register indirection                     MOV AX , [BX]
	c)	 Register Relative Addressing                     MOV AX , [SI + 100]
	d)	 Base plus indexed addressing                   MOV AX , [BX + SI]
	e)	 Relative base plus indexed addressing               MOV AX , [BP + SI + 100]
	f)	 Relative indexed addressing with scale factor         IMUL EBX , [ESI * 4 + 7]
	g)	 Indexed addressing of base address plus scale factor           MOV EAX , [EBX][ESI * 4]
	h)	 Relative base address plus scale factor indexing addressing     MOV EAX , [EDI * 4][EBP + 80]

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2. Instructions for attention MOV— The judgment question must come out

a)	 Data cannot be transferred between two memory units 
b)	 You cannot send data from one segment address register to another segment address register 
c)	CS、IP、EIP Register cannot be used as destination operand 

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Chapter four

1. Random access memory RAM

a.	SRAM 
	a)	 Triggers make up 
b.	DRAM
	a)	 Capacitance composition 

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2. read-only memory ROM— There may be short answer questions

a.	 Mask type ROM
b.	 Programmable read only memory PROM
c.	 Erasable 、 Programmable read only memory EPROM
d.	 Programmable read only memory that can be electrically erased E2PROM
e.	 flash memory 

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3. Generation method of memory chip selection signal ,, Simple questions are frequent visitors , Advantages and disadvantages , Principle and characteristics

a.	 Line selection 
	a)	 The circuit is simple 
	b)	 Directly use the address line as the chip selection signal , Choose a chip for each address 
	c)	 For small capacity 、 In small systems with few memory chips 
	d)	 The addresses of the whole memory are discontinuous , It's a waste of space 
	e)	 The same unit can correspond to different addresses 
b.	 Full decoding method 
	a)	 The storage unit is unique , There will be no address overlap 
	b)	 As long as the choice is good , It can ensure the continuity of addresses 
	c)	 The circuit is complex 
c.	 Partial decoding method 
	a)	 Simplify the decoding circuit , Easy to implement 
	b)	 There will be the problem of address overlap , Waste space 
	c)	 If well organized , It can also ensure the continuity of the address 
d.	 Hybrid decoding method 
	a)	 Because it includes line selection , So there are also the problems of address discontinuity and address overlap 

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4. Memory capacity expansion method —- Completion

a.	 Expansion of data width 
b.	 Byte expansion 

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5. Memory is accessed by word — Judge, choose, fill in the blank

a.	 Alignment state 
	a)	 The starting address is required to be an even address 
b.	 Misaligned state 
	a)	 Because the address provided for word access is an odd address 

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6.Cache Organization style ( characteristic 、 The general principle ) ( master )– Short answer questions usually come out

a.	 All in one way 
	a)	 A block of main memory may be mapped to Cache Anywhere in the world 
b.	 Direct mapping 
	a)	 A block of main memory can only be mapped to Cache A corresponding place of 
c.	 Group connection mode 
	a)	 take Cache Divided into several routes with equal capacity , Each path contains many groups , In every way , The number and number of groups are the same , Each group contains 1 One or more blocks .
	b)	 A block of main memory can only be mapped to Cache Block with specified group number and block number , But it can be mapped to corresponding blocks in different paths 

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The fifth chapter

1. Interfaces are classified by function

a.	 send CPU Auxiliary circuits required for normal operation 
b.	 Input / Output interface 

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2.CPU And the input / Output signals between devices – Remember it , There must be a choice to fill in the blank

a.	 Data and information 
b.	 State information 
c.	 Control information 

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3.I/O port

 Definition ：CPU When transmitting data with peripherals , All kinds of information enter different registers in the interface 
 Addressing mode ： Unified addressing mode and memory I/O Port independent addressing mode 

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4.CPU Data transfer mode between and peripherals ( principle 、 characteristic ) ( master ) Be sure to test , It's a bit of a mystery , It's not organized

a.	 Procedure  
	a)	 Conditional transfer mode 
	b)	 Unconditional transmission mode 
b.	 Interrupt mode 
c.	DMA The way 
	a)	 characteristic 
	i.	 It is an interface circuit  
	ii.	 Able to control the system bus 
	iii.	 Manipulate data transmission between peripherals and memory 

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Chapter six

1. The way of serial communication

a.	 Divide according to the direction 
	a)	 Half duplex mode 
	b)	 Simplex mode 
	c)	 Full duplex mode 
b.	 Divide according to data format 
	a)	 Synchronization mode   （ Sync character    Two at most ）   Both communication parties require the same clock signal 
	b)	 Asynchronous way   （ A start bit , Stop bit （1 , 1.5 , 2）, Parity bit ） 

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2. Programmable serial communication interface 8251A Basic performance

a.	 Synchronization mode 
	a)	 You can use 5、6、7 and 8 Bits to represent characters 
	b)	 It can automatically detect synchronous characters , To achieve synchronization 
	c)	 It is allowed to add parity bit for verification in synchronous mode 
b.	 Asynchronous way 
	a)	 Also available 5、6、7 and 8 Bits to represent characters 
	b)	 use 1 Bit as parity bit 
	c)	 In the asynchronous mode, automatically add a startup bit for each data , And add 1 individual 、1.5 Or 2 Stop bits 

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3.8251A The initialization ( master ) Have a good look

4.8251A In asynchronous mode, the relationship in the mode register ,,, Fill in the blanks

 clock frequency  =  Baud rate factor  *  Baud rate 
8251  Internal address   c/d 
TxD    Data sending   
RxD    Data reception 

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5. Programmable parallel communication interface 8255A, Be sure to test , believe me ,100% Programming questions

a.	 internal structure 
	a)	3 individual 8 Bit data port ：  port A、  port B、  port C
	b)	 port C Through the control command is divided into two 4 Bit port , Respectively used to give ports A And port B Provide control signals and status signals 
b.	 Control word 
	a)	 Mode selection control word 
	b)	 Port you C Set up 1 /  Set up 0 Control word 
c.	 Operation mode 
	a)	 The way 0、 The way 1、 The way 2
	b)	 port A It can work in any of three ways 
	c)	 port B Can only work in the way 0 Or the way 1
	d)	 port C Mating port A And port B Work 
	e)	 Port only A Work in the way 2
d.	 Application example ( master ) ( master ) ( master )
	a)	 As the interface to connect the printer   textbook 233 page 
	b)	 To transmit data 

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Chapter vii. 1.8259A Programming structure ( master )

a.	 control section 
	a)	4 individual 8 Bit register , Store initialization command word ICW1-ICW4 
	b)	3 individual 8 Bit register , Store operation command words OCW1-OCW3  
b.	 Processing parts 
	a)	 Interrupt request register IRR  （ preservation 8 An interrupt message ）
	b)	 Interrupt priority arbiter PR    （ Compare priority size ）
	c)	 Current interrupt service register ISR     （ Record ）

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2.8259A How it works , How to set priorities ( characteristic 、 principle ) ( master ) ( master ) Short answer

a.	 Fully nested 
	a)	 The most common way of working , Interrupt requests are prioritized 0~7 To deal with ,0 Highest level ,7 Lowest level 
	b)	 The interrupt priority arbiter compares the received interrupt request with the current interrupt service register IS A bit more , Determine whether the newly received interrupt has a higher priority than the current interrupt being processed , " , Then interrupt nesting 
b.	 Special nesting 
	a)	 Compared with the fully nested method , There's only one difference , When processing an interrupt at a certain level , If there is a peer interrupt request , Will also respond 
c.	 Priority automatic cycle mode 
	a)	 It is generally used when multiple interrupt sources in the system have the same priority .
	b)	 In this way , Priority queues are variable , After a device is interrupted , Its priority is automatically reduced to the lowest 
d.	 Priority special loop mode 
	a)	 Compared with priority automatic cycle , It's just a little different , At the beginning, the lowest priority and the highest priority are determined by programming .

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3. How many? 8259A Cascading can control several interrupts – Frequent visitors to fill in the blanks

1 A control  8  A break 
2 A control  8 – 1 + 8 = 15
3 A control  8 – 2 + 8 * 2 = 22
4 A control  8 – 3 + 8 * 3 = 29
X A control  8 – x + 8 * （x - 1） = ?      x <= 8

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####4.8259A Initialization process of ( master ) ( master )- Remember it

 Initialization instructions ：
1.ICW1 Write even port ,ICW2～ICW4 Write odd port 
2.ICW1～ICW4 The setting order of is fixed   （16 Bit and 32 Bit system ,ICW4 You have to set ; Only in the case of cascading , Set up ICW3）
3.ICW1 and ICW2 Required ,ICW3 and ICW4 Not necessary  
4. When cascading , Master and slave are set respectively ICW3
5. For each 8259A,ICW1 and ICW2 It must be set 
ICW3  Is set to the high of the interrupt type number 5 position , The lower three digits of the interrupt type number determine which pin the interrupt request enters from 

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Chapter viii.

1.DMA Controller initialization

a.	 Send the start address or end address of the data transmission buffer to the address register 
b.	 Number of bytes to be transferred 、 Word count or double word count is sent to the counter 

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2.8237A Programming structure

 Maximum transmission in the channel 64KB
a.	4 It's a separate channel , Each channel contains 
	1). Current address register   16 position 
	2）. Basic address register   16 position 
	3）. Current byte counter   16 position 
	4）. Basic byte register   16 position 
	5） Mode register   8  position 
b.	4 Channel common control register and status register 

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3.8237A The matching pin of each signal changes during operation ( master ) Be sure to test , textbook 261 page

a.	 When working as a slave module 
b.	 When working as a main module      Address 16 position 

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4.8237A Working mode of

a.	 Single byte transmission mode 
b.	 Block transfer mode 
c.	 Request transfer mode 
d.	 Cascade transmission mode 

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Chapter nine 1.16 Bit counter range

	 Binary system   Maximum 65536
	BCD code   Maximum 10000

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2.8253/5254 Working mode of

a.	 timing 
	a)	 Pattern 2	 Frequency divider     Periodic pulses 
	b)	 Pattern 3	 Square wave generator 
b.	 Count 
	a)	 Pattern 0	 The count ends with an interrupt 
	b)	 Pattern 1	 Programmable monostable trigger 
	c)	 Pattern 4	 Software triggered strobe signal generator 
	d)	 Pattern 5	 Hardware triggered strobe signal generator 

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3.8253/5254 Application examples of ( Programming questions ) ( master ) ( master ) ( master ) The second required programming question , come on.

Chapter ten

1.D/A converter Method a,b And characteristics

a.	 Composed of parallel resistors and operational amplifiers DA converter     Each resistance is different 
b.	T Type weight resistor network and operational amplifier     Only R  and 2R    （ Most common ）
c.	DA Indicators of the converter 
	a)	 The resolution of the     Reflects D/A The sensitivity of the converter , It refers to the ability to distinguish the minimum voltage increment 
	b)	 Conversion accuracy     Absolute conversion accuracy （ Degree of ）、 Relative conversion accuracy （ physical quantity ）
	c)	 Conversion rate and setup time    Reaction conversion rate  
	d)	 Linear error     

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2.A/D converter

a.	AD Parameters involved in conversion 
	a)	 The resolution of the       The ability to distinguish the smallest signal 
	b)	 Conversion accuracy        Reflects A/D The accuracy of the actual value of the converter is close to the ideal value 
	c)	 Conversion rate           Finish once A/D The reciprocal of the time required for the converter 
b.	AD Methods and characteristics of transformation 
	a)	 Counting type AD transformation       Simple , Slow speed 
	b)	 Biproduct fraction AD transformation      Strong anti-interference ability  ,  It's not fast 
	c)	 Step by step AD transformation       The fastest 
	d)	 Use software and DA Converter to achieve AD transformation    Faster 

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Chapter 11

1. Keyboard structure

a.	 The simplest keyboard structure    ---  Pin connection 
b.	 Matrix structure of keyboard    ---- Matrix connection 

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2. Key recognition

a.	 Line scan 
b.	 Row reversal 

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Chapter 15 1. Classification and application of computer bus common

a.	 Internal bus    cpu Bus 
	a)	 It is used to connect the on-chip arithmetic unit, registers and other major components 
	b)	 Also called on-chip bus 
b.	 Local bus    PCI  ISA EISA
	a)	 Connect the main components on the motherboard 
	b)	 Various adapters can be connected through expansion slots , Such as   card , Sound card 、 network card 、 Image card, etc 
c.	 The system bus 
	a)	 Connect the CPU Plug in boards and other bus master modules 
	b)	 The most popular system bus is MULTIBUS、STDBUS and VME
d.	 External bus    USB   SCSI   RS-232-C   EIDE 
	a)	 Communication bus between microcomputer and peripherals 

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2. Performance index of bus

a.	 Width 	 The number of data bits that can be transmitted at one time 
b.	 Bus frequency 	 The number of times that data can be transmitted per second when the bus is working 
c.	 Transmission rate 	 The number of bytes that can be transmitted per second when the bus is working 

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