How to become a senior digital IC Design Engineer (1-3) Verilog coding syntax: Verilog behavior level, register transfer level, gate level (abstract level)

One 、 Behavior level （Behavior Level）

        1、 More advanced , Mainly used for simulation verification 、 System behavior 、 Algorithm description , It's not about circuit implementation .

        2、 The function description mainly adopts high-level language structure , Such as task、function.

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Two 、 Register transfer level （Register Transfer Level）

        1、 It's lower , It is mainly used for ASIC and FPGA Design , Lies in the circuit implementation , Focus on describing the data flow and control flow within or between function blocks .

        2、 The function description mainly adopts a comprehensive language structure , Such as always、assign.

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3、 ... and 、 Gate level （Gate Level）

        1、 Lower level , It is mainly used for IC Physical implementation of the back end , lie in ASIC and FPGA Development of small-scale components .

        2、 The function description mainly adopts logic gates 、 User defined primitives 、 Module and network connection , Such as and、or、not.

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Four 、 Design consistency

         Numbers IC The task of the design engineer , It can be understood as transforming a IDEA perhaps SPEC Design for Physics （ASIC、FPGA）, Excellent numbers IC Design engineers can have good Verilog Encoding style ,100% Ensure the consistency of pre simulation and post simulation of the design （Presynthesis and Postsynthesis）, meanwhile 100% Ensure that the design can be synchronously transferred to simulation and synthesis . otherwise , Easy when the chip has been produced , Only to find that the chip can't work properly , Then start designing again , Secondary projection （TapeOut）.