[Verilog quick start of Niuke network question brushing series] ~ asynchronous reset Series T trigger

0. Preface

Today, I only scratched one question , Why? ？ Is it because it's hard ？ It doesn't seem to be ！！！ Because I think the question on niuke.com seems to be full of loopholes , So I came up with a bold idea , That is to write your own design and test files , Use vcs+verdi Co simulation （ Follow the crowd , Ha ha ha ）. Let's not say anything else , It took me a day just to pretend , Purring . But now the environment is basically no problem , About the environment , I did it with reference to the boss , See references .

1. Asynchronous reset series T trigger

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1.1 Title Description

use verilog Realize two asynchronous reset in series T Logic of trigger

1.1.1 Signal schematic diagram

1.1.2 Waveform diagram

1.1.3 Input description

Input signal data, clk, rst
type wire
stay testbench in ,clk For cycles 5ns The clock of ,rst Reset for low level

1.1.4 Output description

The output signal q
type reg

1.2 Their thinking

It should be noted that , What is the effective level of each signal ？ We need to make this clear according to the requirements of the topic , What I need to roast about here is , It is a low level reset , It is not officially defined as rst_n（_n The default is that the low level is active , Personal habits ）.

Knowledge point 1：T trigger ===> Input is 1, Output flip ; Input is 0, Output hold .

Knowledge point 2： Asynchronous reset means that the reset can be completed without waiting for the clock . meanwhile , And synchronous reset , In general , It is best to use synchronous reset , Sometimes, asynchronous reset cannot be avoided , Because it saves resources , Very provincial , ha-ha , therefore , An asynchronous reset has occurred , Synchronous release operation , extensive use .

1.3 Code implementation

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg q_reg;
    
    always @ (posedge clk or negedge rst) begin
        if(!rst) begin
           q_reg <= 1'b0; 
        end
        else begin
            if(data) begin
               q_reg <= ~q_reg; 
            end
            else begin
               q_reg <= q_reg; 
            end
        end
    end
    
    always @ (posedge clk or negedge rst) begin
        if(!rst) begin
           q <= 1'b0; 
        end
        else begin
            if(q_reg) begin
               q <= ~q; 
            end
            else begin
               q <= q; 
            end
        end
    end

//*************code***********//
endmodule

1.4 Simulation file

About simulation files , I haven't done it yet , Let me familiarize myself with vcs and verdi A combination of , ha-ha ！ Coming soon .

1.5 Simulation waveform

Coming soon ！！！

reference

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