Arm debug interface (adiv5) analysis (I) introduction and implementation [continuous update]

I am a Snow fish , a FPGA lovers , The research direction is FPGA Architecture exploration and SOC Design .

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One 、ADIv5 brief introduction

ADI yes Arm Used to connect and use inline CoreSight framework SoC Interface of commissioning function , The latest version is ADIv6, What I use in my current job ADIv5, So first ADIv5 To study .
ADIv5 There are two main components ：

• Access Port(AP):ADIv5.0 Two are defined AP, namely JTAG-AP and MEM-AP
  1. JTAG-AP: visit JTAG equipment
  2. MEM-AP: visit memory Or with memory-mapped Components of the interface
• Debug Port(DP): ADIv5.0 Two are defined DP, namely JTAG-DP and SW-DP

Two 、ADIv5 The implementation of the

ADI How to implement , The actual module , go by the name of Debug Access Port (DAP).DAP Provide standard interfaces for external debuggers , Such as JTAG/SW To visit SoC Debugging resources in . The schematic diagram is shown in the figure below ：

One DAP The following components are required to support JTAG Scan chain .

• One Debug TAP State Machine (DBGTAPSM), It's actually TAP, Make a state transition , Yes IR and DRs To operate .
• One Instruction register(IR), Select and control available scan chains
• Multiple Data register（DRs）, stay DRs Accessible debugging related data is stored in , There are two main categories
  1. DAP Component's DR
  2. By DAP Access the debug component or JTAG In the equipment DR

Physical layer connection mode ：

2.1 JTAG-DP

External debuggers can be implemented by IEEE1149.1 JTAG The standard DBGTAP Scan the chain to access JTAG-DP , Read and write related register data . JTAG-DP Is based on IEEE 1149.1 Standard for Test Access Port (TAP) and Boundary Scan Architecture canonical , But the names are different ：

IR The width of can be defined as 4bit perhaps 8bit, The standards that must be realized IR Command value has ：

There are mainly 5 individual IR Command value , Map to the corresponding DR.

（1） DPACC/APACC The purpose of is to use respectively DP and AP Register to read and write .

• DPACC The scanning chain adopts

A[3:2], SELECT.DPBANKSEL , RnW

To decide what to visit DP The address of the register .DP The register has ;

DPACC and APACC The seat widths are 35bit .

Scan chain operation ：
When IR Choose DPACC perhaps APACC when , Will DPACC/APACC Register is placed in DBGTDI and DBGTDO Scan the chain , As shown in the figure below ：

• Capture-DR state ： Grab the last operation result onto the scan chain and output , The result of this operation has 3 bit Response data for ACK. There are two kinds , It is divided into OK/FAULT and WAIT The definition is as follows ：