Load/store instruction addressing mode of arm instruction set (1)

This note records the operation 32 Bit type and unsigned byte data Load/Store The addressing mode used by the instruction .

All types of Load/Store The addressing mode of instructions is determined by Base address Add Offset Composed of , The base address is specified in any general-purpose register , There are three ways to specify the offset ：

1. Count now ;
2. register ;
3. Register and a shift constant ;

There are three ways to calculate the addressing mode ：

1. Offset method ;
2. Update the method beforehand ： Calculate the access address first , Then access storage , Finally, update the base register with the memory access address , It is also called after the fact visit （ After the event means that the address is updated after the memory access operation ）;
3. Post update method ： First, use the base register value to access , Then calculate the new memory access address , Finally, update the base register with the new memory access address , Also known as prior access （ It means that the memory access operation precedes the address update ）;

Be careful ： The above applies to all types of Load/Store Instructions .

Grammar format

operation 32 Bit type and unsigned byte data Load/Store The syntax format of the instruction is as follows ：

LDR{<cond>}{B} {T}<Rd>, <address_mode>

• B Indicates that the operation is an unsigned byte ;
• T Indicates that the instruction is executed with user mode permission , See instruction introduction for details .

Addressing mode

operation 32 Bit type and unsigned byte data Load/Store Instruction common 9 Address mode , Let's talk about each of them .

	grammar	explain
1	[<Rn>, #+/-<offset_12>]	Immediate offset addressing
2	[<Rn>, +/-<Rm>]	Register offset addressing
3	[<Rn>, +/-<Rm>, <shift>#<shift_imm>]	Register shift offset addressing
4	[<Rn>, #+/-<offset_12>]!	Immediate pre update addressing
5	[<Rn>, #+/-<Rm>]!	Register pre update addressing
6	[<Rn>, +/-<Rm>, <shift>#<shift_imm>]!	Register shift pre update addressing
7	[<Rn>], #+/-<offset_12>	Immediate post update addressing
8	[<Rn>], +/-	Register post update addressing
9	[<Rm>], +/-<Rn>, <shift>#<shift_imm>	Register shift post update addressing

Immediate offset addressing

[<Rn>, #+/-<offset_12>]
 
if U == 1 then
	address = Rn + offset_12
else
	address = Rn - offset_12

Register offset addressing

[<Rn>, +/-<Rm>] 

if U == 1 then
	address = Rn + Rm
else
	address = Rn - Rm

Register shift offset addressing

[<Rn>, +/-<Rm>, <shift>#<shift_imm>]

according to <shift> Different , There are several shift offset addressing methods in total ：

 Logic shift left ：[<Rn>, +/-<Rm>, LSL #<shift_imm>]
 Logical shift right ：[<Rn>, +/-<Rm>, LSR #<shift_imm>]
 Count right ：[<Rn>, +/-<Rm>, ASR #<shift_imm>]
 Cycle moves to the right ：[<Rn>, +/-<Rm>, ROR #<shift_imm>]
 The extended loop moves to the right ：[<Rn>, +/-<Rm>, RRX]

case LSL:
	index = Rm LSL shift_imm
case LSR:
	if shift_imm == 0 then 		//  Move right 32 position 
		index = 0
	else
		index = Rm LSR shift_imm
case ASR:
	if shift_imm == 0 then		//  Move right 32 position 
		if Rm[31] == 1 then
			index = 0xFFF_FFFF
		else
			index = 0
	else
		index = Rm ASR shift_imm
case ROR | RRX
	if shift_imm == 0 then		// RRX
		index = (C Flag LSL 31) OR (Rm LSR 1)
	else 		// ROR
		index = Rm ROR shift_imm

if U == 1 then
	address = Rn + index
else
	address = Rn - index

Immediate pre update addressing

[<Rn>, #+/-<offset_12>]!

if U == 1 then
   address = Rn + offset_12
else
   address = Rn - offset_12
if CondPassed then
   Rn = address

Register pre update addressing

[<Rn>, #+/-<Rm>]!

if U == 1 then
	address = Rn + Rm
else
	address = Rn - Rm
if CondPassed then
	Rn = address

Register shift pre update addressing

 [<Rn>, +/-<Rm>, <shift>#<shift_imm>]!

Allied , according to <shift> Different , There are several shift offset addressing methods in total ：

 Logic shift left ：[<Rn>, +/-<Rm>, LSL #<shift_imm>]!
 Logical shift right ：[<Rn>, +/-<Rm>, LSR #<shift_imm>]!
 Count right ：[<Rn>, +/-<Rm>, ASR #<shift_imm>]!
 Cycle moves to the right ：[<Rn>, +/-<Rm>, ROR #<shift_imm>]!
 The extended loop moves to the right ：[<Rn>, +/-<Rm>, RRX]!

case LSL:
	index = Rm LSL shift_imm
case LSR:
	if shift_imm == 0 then 		//  Move right 32 position 
		index = 0
	else
		index = Rm LSR shift_imm
case ASR:
	if shift_imm == 0 then		//  Move right 32 position 
		if Rm[31] == 1 then
			index = 0xFFF_FFFF
		else
			index = 0
	else
		index = Rm ASR shift_imm
case ROR | RRX
	if shift_imm == 0 then		// RRX
		index = (C Flag LSL 31) OR (Rm LSR 1)
	else 		// ROR
		index = Rm ROR shift_imm

if U == 1 then
	address = Rn + index
else
	address = Rn - index
if CondPassed then
	Rn = address

Immediate post update addressing

[<Rn>], #+/-<offset_12>

address = Rn
if CondPassed then
	if U == 1 then
		Rn = Rn + offset_12
	else
		Rn = Rn - offset_12

Register post update addressing

[<Rn>], +/-<Rm>

address = Rn
if CondPassed then
	if U == 1 then
		Rn = Rn + Rm
	else
		Rn = Rn - Rm

Register shift post update addressing

[<Rm>], +/-<Rn>, <shift>#<shift_imm>

Allied , according to <shift> Different , There are several shift offset addressing methods in total ：

 Logic shift left ：[<Rn>], +/-<Rm>, LSL #<shift_imm>
 Logical shift right ：[<Rn>], +/-<Rm>, LSR #<shift_imm>
 Count right ：[<Rn>], +/-<Rm>, ASR #<shift_imm>
 Cycle moves to the right ：[<Rn>], +/-<Rm>, ROR #<shift_imm>
 The extended loop moves to the right ：[<Rn>], +/-<Rm>, RRX

address = Rn
case LSL:
	index = Rm LSL shift_imm
case LSR:
	if shift_imm == 0 then 		//  Move right 32 position 
		index = 0
	else
		index = Rm LSR shift_imm
case ASR:
	if shift_imm == 0 then		//  Move right 32 position 
		if Rm[31] == 1 then
			index = 0xFFF_FFFF
		else
			index = 0
	else
		index = Rm ASR shift_imm
case ROR | RRX
	if shift_imm == 0 then		// RRX
		index = (C Flag LSL 31) OR (Rm LSR 1)
	else 		// ROR
		index = Rm ROR shift_imm

if CondPassed then
	if U == 1 then
		Rn = Rn + index
	else
		Rn = Rn - index