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MediaTek 2023 IC written examination approved in advance (topic)
2022-07-03 04:37:00 【Trip of Jie】
Preface
- First , Thank you for sharing this article !
- Statement : Personally feel , Learning period , Basically, it is the transportation of knowledge , So all the content of this blog can be quoted ! For your convenience , The pictures in the blog are not watermarked by the blog ( Unless you don't own it or don't see it )!
- If everyone feels that their basic knowledge is weak , You can go to 《 Niu Ke brush questions 》 and 《HDLbits》 Practice consolidation ; If you don't understand the topic, you can also refer to the article 《 Niuke brush verilog》Part I Verilog Quick start and verilog practice :hdlbits The website series is over ! To study !
1.
1、(8 branch )【 Short answer 】 The following is a paragraph verilog Code , Please follow the description of the code , Combined with known clk and rst_b Oscillogram of , Draw the waveform of the corresponding signal .(8 branch )
reg [1:0]cnt;
wire [1:0]cnt_nxt = cnt - 2'b1;
wire out_1 = &cnt_nxt;
wire out_2 = cnt_nxt[0+:1];
[email protected](posedge clk or negedge rst_b)begin
if(~rst_n) cnt <= 2'h3;
else cnt <= cnt_nxt;
end
2. Logic diagram simplification
- Probably
((AB)' · (A'·B')' )'
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Postscript
- Welcome to reprint the title !
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