Chapter 6 data flow modeling

Continuous assignment

• The continuous assignment statement is verilog The basic statement of data flow modeling , Used to deal with Wire network Assign a value .

• This thing is equivalent to gate level description , But it describes the circuit from a higher abstract point of view .

• Consecutive assignment statements must be in the form of the keyword assign Start .

• Continuous assignment statements have the following characteristics ：

  • The value on the left must be a scalar / Vector network / The splicing of scalar and vector line nets , Choose one of the three , It cannot be a vector or a vector register .
  • Always active , As long as one operand changes , The expression is immediately recalculated , Reassign .
  • Operands can be scalars / Vector nets or registers / Function call .
  • The assignment delay can be used to control the time when a new value is assigned to the network , Similar to door delay .

• give an example

  //out It's a network ,in1, in2 It is also a network 
  assign out = in1 & in2;	
  
  // addr yes 16 Bit vector line network 
  // addr1_bits, addr2_bits All are 16 Bit vector register 
  assgin addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0];
  
  //  Splicing 
  assign {
        c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
  

Implicit continuous assignment

• See this hidden word , I know , There must be something missing .

• Online statement at the same time , Assign a value to it . The network can only be declared once , Therefore, there can only be one implicit continuous assignment .

  //  Normal assignment 
  wire out;
  assgin out = in1 & in2;
  
  //  It is equivalent to 
  wire out = in1 & in2;
  

Implicit network declaration

• Empathy , Since you can hide assgin, That can be hidden wire Do you ？

• Of course, it can be

  // out No network statement is made for it , The simulator will infer out Is an implicitly declared network 
  wire in1,in2;
  assgin out = in1 & in2;
  

Delay

• Delay in consecutive assignment statements , Used to control the time interval between any operand changes and the statement lvalue is given a new value （ To put it bluntly , When does the value on the left change , This time can be artificially defined ）.
• Specify the method of assignment delay ：
  • Normal assignment delay
  • Implicit continuous assignment delay
  • Network declaration delay

Delay of ordinary assignment

• Specify the value of the delay in the continuous assignment statement , The delay value is located at assgin Back .

  assgin #10 out = in1 & in2;
  

• Inertia delay ： In the example above ,in1 & in2 The new value of , Before assigning to the left , Yes 10 Time unit delay , If in this 10 In units of time ,in1 & in2 The value of has changed again , The new value of the assignment expression is retrieved in1 & in2 The current value of the . This property is inertia delay .
  
• As shown in the figure , Signals smaller than the delay time are shielded , Because I just planned 10 Time unit assignment 1 to out, result in1 I become 0 了 , therefore out by 0. It can be used to shield pulse signals with short time .

Delay of implicit continuous assignment

• Empathy , The concept is the same , It's just that the assignment method has changed .

  //  Implicit continuous assignment 
  wire #10 out = in1 & in2;
  
  //  Equivalent to 
  wire out;
  assign #10 out = in1 & in2;
  

Delay of network declaration

• Empathy , The concept is the same

  //  Network delay 
  wire #10 out;
  assgin out = in1 & in2;
  
  //  Equivalent to 
  wire out;
  assign #10 out = in1 & in2;
  

expression

• Data flow modeling uses expressions to describe the design . expression 、 Operators and operands are the basis of data flow modeling .

• expression ： Composed of operators and operands , The purpose is to calculate a result according to the meaning of the operator .

  a ^ b 
  addr[20:17] + addr[20:17]
  in1 | in2 
  

• Operands ： Operands can be any data type defined ,

• The operator ： An operation on an operand produces a result .

Operator type

• There are several types of operators ： The arithmetic 、 Logic 、 Relationship 、 Equivalent 、 Bitwise 、 cut 、 displacement 、 Splicing and conditional operators .
  
• Pick a few unfamiliar records

Equivalent operator

• Relevant instructions are shown in the figure
  

Reduction operator

• There is only one operator , Operate on vector operands bit by bit , Produce one by one results .
  

Conditional operators

• With three operands , usage ：

  condition_expr ? true_expr : false_expr;
  

• namely ： Evaluate conditional expressions , If it is true , The calculation true_expr; For false , Calculation false_expr; For uncertainty x, Then both expressions are evaluated , Then the two results are compared bit by bit . If equal , Then the value of this bit in the result is the value of this bit in the operand ; If you don't want to wait , Then the value of this bit in the result is x.

• Conditional expressions are similar to multiplexers
  

• Be careful ：if-else You can replace conditional expressions , But only in block statements , Cannot replace .

priority

• It is recommended to separate the expressions with parentheses .
  

give an example

Choose a multi-path selector

• Here's the picture , This is the door level modeling description learned earlier
• Use logical equations to describe
  
• Use the conditional operator
  
• so , Modeling with data flow is very simple .

Four position full adder

• Empathy , Use data flow operation statements to describe a four bit full adder
  

Pulse carry counter

summary