Communication between DSP and FPGA

I've been curious before DSP and FPGA How does the address of correspond to the past .

（1）： Configure the pins first ：

void InitXintf16Gpio() //16 position ;
{
     EALLOW;
     GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;  // XD15
     GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;  // XD14
     GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;  // XD13
     GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;  // XD12
     GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;  // XD11
     GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;  // XD10
     GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;  // XD19
     GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;  // XD8
     GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;  // XD7
     GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;  // XD6
     GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;  // XD5
     GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;  // XD4
     GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;  // XD3
     GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;  // XD2
     GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;  // XD1
     GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;  // XD0

     GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;  // XA0/XWE1n
     GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;  // XA1
     GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;  // XA2
     GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;  // XA3
     GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;  // XA4
     GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;  // XA5
     GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;  // XA6
     GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;  // XA7

     GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;  // XA8
     GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;  // XA9
     GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;  // XA10
     GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;  // XA11
     GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;  // XA12
     GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;  // XA13
     GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;  // XA14
     GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;  // XA15
     GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // XA16
     GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;  // XA17
     GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3;  // XA18
     GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // XA19  

     //GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3;  // XREADY
     //GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3;  // XRNW
     GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;  // XWE0

     GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;  // XZCS0
     GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;  // XZCS7
     //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // XZCS6
     EDIS;
}

In fact, everyone who is configured as a data bus has been determined to be dead . Such as pin 79 Can only be configured as data bits 0 Number is , The address line is also , As for the number of address lines to use , This is freedom , But generally speaking, the data bits should be 16 Bit , perhaps 32 A data . That's it DSP The wiring of . When giving an address area 0 No. 1 of （0x004000） When you write data , Due to the same addressing, it will DSP Will give 0x00 0000 That is, give each address bus a low potential , Not the actual （0x00 4000） Output directly to the address bus .

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（2） Here is FPGA The wiring of the cable , stay pin_planner Pin arrangement in .

  The pin arrangement is as follows ：

  stay FPGA The address vector defined in will address 0 To pin 28, Put the address pin 1 to 25, And so on .

  Finally, the write instruction will be executed , Writes data to memory（） among .

So that's the end of it DSP Address in 0x00400(0 Address ) The variable of is passed to FPGA Of memory（0） Communication in .

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（3） Continue to write about how to synchronize carriers

            if(memory(0)=0)then                    --clear ready signal;
                ready<=0;
            end if;    
            
            if(memory(0)=1)then             --set ready signal;
                ready<=ready+1;
            elsif(ready=1)then
                ready<=2;
                end if;
            
            if((we='1')and(memory(0)=1))then
                memory(0)<=0;             
            end if;

After the initialization memory(0)=0;ready=0; When memory be equal to 1, That is to say DSP When the synchronization signal is sent ,ready=1; This step triggers two parallel processes , It is further changed into 2（ Due to parallel triggering , Prevent further triggering of other signals ）, In the next step memory Set up 0, Then there will be ready Set up 0, Form a closed loop .

        if(clk'event and clk='1')then
        
            -- Carrier start data update
            if(ready=1)then   

                sector<=memory(2);
                t1<=memory(3);--dap
                t2<=memory(4);--dbp
                mode<=memory(5);
                t3<=memory(6);--dan
                t4<=memory(7);--dbn    
                                    
            end if;  

  And the following ：

        begin
           if(reset='0')then
              count<=0;
           elsif(clk'event and clk='1')then
                  if(ready=1)then
                        count<=0;
                elsif(count>=(ts-1))then
                  count<=(ts-1);
               else 
                       count<=count+1; 
                  end if;               
           end if;

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（4） An error occurred in the programming process ：Error (10531): VHDL Variable Declaration error at basic.vhd(56): variable declared outside subprogram or process must be a shared variable

Here because of the right VHDL Medium variable  and signal  The reason for not understanding well . I define it directly in

  Here is not in architecture Of variables defined in . This proves that , there signal Several processes will be linked , Once a change occurs, multiple variables will be triggered , This is a signal and   variable The difference between .

（5） Multiple vhdl Cooperation of physical time ：

With count As an example , In an entity count Count , But in another PWM.vhd In the middle of PWM Generation in . How to call . This needs to be in the counting entity , Set up count For the output port , stay PWM.vhd The entity will count Set as input port .