【QPSK中频】基于FPGA的QPSK中频信号产生模块verilog设计

1.软件版本

matlab2013b+quartusii

2.本算法理论知识

QPSK信号可以表示为：

QPSK信号的组成方框图如图1所示。

 下面，我们将基于这个结构设计一个QPSK调制信号发送模块。

3.部分源码

`timescale 1ns / 1ps
module tops(
            i_clk,
            i_rst,
				o_signal,
				o_I,
				o_Q,
				o_I_filter,
				o_Q_filter,
				o_I_cos,
				o_Q_sin,
				o_R
            );

input              i_clk;
input              i_rst;
output             o_signal;
output signed[1:0] o_I;
output signed[1:0] o_Q;
output signed[15:0]o_I_filter;
output signed[15:0]o_Q_filter;
output signed[15:0]o_I_cos;
output signed[15:0]o_Q_sin;
output signed[15:0]o_R;

wire clk4m;
wire clk8m;
DCM DCM_u(
          .i_clk     (i_clk),
			 .i_rst     (i_rst),
			 .o_clk_8m1 (clk4m),
			 .o_clk_8m2 (clk8m)
          );
			  
signal signal_u(
              .i_clk (clk4m),
              .i_rst (i_rst),
				  .o_dout(o_signal)
              );

s2p s2p_u(
           .i_clk    (clk4m),
			  .i_clk2   (i_clk),
			  .i_rst    (i_rst),
			  .i_signal (o_signal),
			  .o_I      (o_I),
			  .o_Q      (o_Q)
          );

filter filter_u1(
                .i_clk (i_clk),
				    .i_rst (i_rst),
				    .i_din (o_I),
				    .o_dout(o_I_filter)
               );			 
			 
filter filter_u2(
                .i_clk (i_clk),
				    .i_rst (i_rst),
				    .i_din (o_Q),
				    .o_dout(o_Q_filter)
               );				 

					
					
wire signed[15:0]fsin;
wire signed[15:0]fcos;					 
					 
NCO_ip NCO_ip_u(
	         .phi_inc_i (16'd16384),
	         .clk       (i_clk),
	         .reset_n   (~i_rst),
	         .clken     (1'b1),
	         .fsin_o    (fsin),
	         .fcos_o    (fcos),
	         .out_valid ()
	         );

 
reg signed[31:0]r_I_cos;
reg signed[31:0]r_Q_sin; 				 
		
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
	  begin
	  r_I_cos <= 32'd0;
	  r_Q_sin <= 32'd0;
	  end
else begin
	  r_I_cos <= fcos*o_I_filter;
	  r_Q_sin <= fsin*o_Q_filter;
     end
end
assign o_I_cos = r_I_cos[29:14];
assign o_Q_sin = r_Q_sin[29:14];
		
assign o_R = o_I_cos + o_Q_sin;						
					
endmodule 

4.仿真效果

通过设计，整个系统的RTL结构图如下所示：

仿真结果如下所示：

A01-110