Hongke | uses jesd204 serial interface to bridge analog and digital worlds at high speed

1. What is? JESD204 agreement ？

JESD204 The standard is dedicated to the transmission of converter samples through the serial interface .2006 year ,JESD204 The standard supports multiple data converters on a single channel . The following revisions ：A、B、C Support for multi-channel has been added successively 、 Deterministic delay 、 Error detection and correction functions , And continuously improve the channel speed .JESD204 It's widely used , Including telecommunications （ wireless 、 Beamforming 、5G）, Aerospace （ Satellite communications 、 imaging ） And other uses tell ADC or DAC Industry .

2. JESD204 The history of the agreement

3. Converter data oriented framework

JESD Input data parameters
• M - Each linked converter
• S - Samples of each converter
• N - Number of digits per sample （ The resolution of the ）
• CS - Control bit of each sample
• N’ - Sample container N’ >= N+CS

JESD Framing parameters
• L - Channel of each link
• F - In each channel frame 8 Bit byte
• K - MultiFrame (204B) Frame in
• E - Expand multiple blocks in multiple blocks (204C)
• HD - high-density （ Allow the sample to be split ）
• CF - Control frame （ At the end of the frame CS）

The converter samples are continuously combined into a frame , Then split across channels

4. Deterministic delay

JESD204B The deterministic delay introduced in allows the system to reset throughout 、 Constant system delay during power on cycle and reinitialization events . in the majority of cases , This is by providing a system reference signal (SYSREF) To achieve , This signal establishes a common timing reference between the transmitter and the receiver , And allow the system to compensate for any delay variability or uncertainty .

5. Main traps and hidden dangers

around JESD204 The main pitfalls and hidden dangers of system design according to the standard will involve subclasses 1 System clock in , The deterministic delay is achieved by using SYSREF Realized ,SYSREF The generation and utilization under different system conditions are also critical . Choose the correct frame format and SYSREF Type to match the stability of the system clock and link delay is very challenging .
Standardized treatment CRC and FEC The bit order of is not always clear , The technical drawing does not match the truth table , This difference will lead to different implementation methods , Cause incompatibility . Hongke partners Comcores Measures have been taken to prevent these traps and hidden dangers , Such as bit exchange . If you need technical support in this regard , Welcome to contact Hongke technical engineer .

Why choose Hongke Comcores JESD204 IP

Siphonaceae Comcores JESD204 IP Has been in all major OEM plants and as low as 5nm In the process of, many times of flaking were carried out . Besides , The JESD IP Has passed with all major data converters and SerDes/PHY Interoperability testing , Thus, a highly compatible design is achieved .