Named block Verilog

Named blocks

We can name the block statement structure .

Local variables can be declared in named blocks , Access variables through the method of hierarchical name reference .

The simulation code is as follows :

example

`timescale 1ns/1ns
 
module test;
 
    initial begin: runoob   // Name the module as runoob, You can't have less semicolons
        integer    i ;       // This variable can be passed through test.runoob.i Used by other modules
        i = 0 ;
        forever begin
            #10 i = i + 10 ;      
        end
    end
 
    reg stop_flag ;
    initial stop_flag = 1'b0 ;
    always begin : detect_stop
        if ( test.runoob.i == 100) begin //i Add up 10 Time , namely 100ns Stop simulation when
            $display("Now you can stop the simulation!!!");
            stop_flag = 1'b1 ;
        end
        #10 ;
    end
 
endmodule

The simulation results are as follows :

Named blocks can also be disabled , With keywords disable To express .

disable The execution of named blocks can be terminated , Can be used to exit from the loop 、 Handling errors, etc .

And C In language break similar , however break You can only exit the current cycle , and disable You can disable any named block in the design .

The simulation code is as follows :

example

`timescale 1ns/1ns
 
module test;
 
    initial begin: runoob_d // Name the module as runoob_d
        integer    i_d ;
        i_d = 0 ;
        while(i_d<=100) begin: runoob_d2
            # 10 ;
            if (i_d >= 50) begin       // Add up 5 Stop accumulation for times
                disable runoob_d3.clk_gen ;//stop external block: clk_gen
                disable runoob_d2 ;       //stop At present block: runoob_d2
            end
            i_d = i_d + 10 ;
        end
    end
 
    reg clk ;
    initial begin: runoob_d3
        while (1) begin: clk_gen  // Clock generation module
            clk=1 ;      #10 ;
            clk=0 ;      #10 ;
        end
    end
 
endmodule

The simulation results are as follows :

It can be seen from the picture that , The signal i_d Add up to 50 in the future , No longer accumulate , in the future clk The clock is no longer produced .

so ,disable Exited the current while block .

It should be noted that ,disable stay always or forever When used in block, you can only exit the current round , The next statement will still be always or forever In the implementation of . because always Block and forever Blocks are always executed , At this time disable It's kind of similar C In language continue function .