Detailed explanation of the difference between Verilog process assignment

Verilog Process assignment

key word ： Block assignment , Nonblocking assignment , parallel

Procedural assignment is in initial or always Assignment in statement block , The assignment object is a register 、 Integers 、 Types such as real numbers .

These variables are assigned , Its value will remain unchanged , Until a new value is assigned .

Continuity assignment is always active , Any change in the operand will affect the result of the expression ; Procedure assignment only occurs when the statement is executed , It works . This is the difference between continuous assignment and procedural assignment .

Verilog Process assignment includes 2 A kind of sentence ： Blocking assignment and non blocking assignment .

Block assignment

Blocking assignment belongs to sequential execution , That is, before the execution of the next statement , The current statement must be executed .

Blocking assignment statements use the equal sign  =  As an assignor .

In the previous simulation ,initial The assignment statements inside are blocking assignment .

Nonblocking assignment

Non blocking assignment is a parallel execution statement , That is, the execution of the next statement and the execution of the current statement are carried out at the same time , It does not block the execution of subsequent statements in the same statement block .

Non blocking assignment statements use the less than or equal sign  <=  As an assignor .

Use the following code , To block 、 Non blocking assignment for simulation , To illustrate 2 The difference between process assignment .

example

`timescale 1ns/1ns
 
module test ;
    reg [3:0]   ai, bi ;
    reg [3:0]   ai2, bi2 ;
    reg [3:0]   value_blk ;
    reg [3:0]   value_non ;
    reg [3:0]   value_non2 ;
 
    initial begin
        ai            = 4'd1 ;   //(1)
        bi            = 4'd2 ;   //(2)
        ai2           = 4'd7 ;   //(3)
        bi2           = 4'd8 ;   //(4)
        #20 ;                    //(5)
 
        //non-block-assigment with block-assignment
        ai            = 4'd3 ;     //(6)
        bi            = 4'd4 ;     //(7)
        value_blk     = ai + bi ;  //(8)
        value_non     <= ai + bi ; //(9)
 
        //non-block-assigment itself
        ai2           <= 4'd5 ;           //(10)
        bi2           <= 4'd6 ;           //(11)
        value_non2    <= ai2 + bi2 ;      //(12)
    end
 
   //stop the simulation
    always begin
        #10 ;
        if ($time >= 1000) $finish ;
    end
 
endmodule

The simulation results are as follows ：

sentence （1）-（8） Are blocking assignments , Execute in order .

20ns Before , The signal ai,bi Value change . Due to the characteristics of process assignment ,value_blk = ai + bi It didn't work out to , therefore 20ns Before ,value_blk The value is X（ Uncertain state ）.

20ns after , The signal ai,bi Value changes again . Execute to value_blk = ai + bi, The signal value_blk Using signals ai,bi The new value of gets the calculation result 7.

sentence （9）-（12） Are non blocking assignments , Parallel execution .

First ,（9）-（12） Although they are all executed concurrently , But the order of execution is also （8） after , So the signal value_non = ai + bi Computation also uses signals ai,bi The new value of , The result is 7.

secondly ,（10）-（12） It's concurrent execution , therefore value_non2 = ai2 + bi2 When calculating , Don't care about signals ai2,bi2 The latest non blocking assignment result of . namely value_non2 Signals are used in the calculation ai2,bi2 The old value , The result is 4'hF.

Use non blocking assignment to avoid competitive risk

The above simulation code is just for readers to better understand the difference between blocking assignment and non blocking assignment . actual Verilog Code design , Remember not to mix blocking assignment with non blocking assignment in a process structure . When two assignment methods are mixed , Timing is not easy to control , It's easy to get unexpected results .

More time , When designing circuits ,always Multi use non blocking assignment in sequential logic blocks ,always Multiple blocking assignment in combinational logic blocks ; When simulating circuits ,initial Blocking assignment is generally used in blocks .

As shown below , To realize switching on the rising edge of the clock 2 Function of register values , stay 2 individual always Block using blocking assignment .

because 2 individual always The statements in the block are performed simultaneously , however a=b And b=a It is impossible to determine the order of execution , This creates a competitive situation .

But whichever comes first （ It has something to do with compilers ）, Don't consider timing The question is , They always carry out in order , Last a And b The value of is always equal . Failed to reach the exchange 2 Effect of register values .

example

always @(posedge clk) begin
    a = b ;
end
 
always @(posedge clk) begin
    b = a;
end

however , If in always Block using non blocking assignment , Can avoid the above competitive and risky situation .

As shown below ,2 individual always The statements in the block execute in parallel , The right-hand operand of the assignment operation uses the old value of the previous clock cycle , here a<=b And b<=a You can execute without interfering with each other , Achieve the purpose of exchanging register values .

example

always @(posedge clk) begin
    a <= b ;
end
 
always @(posedge clk) begin
    b <= a;
end

Of course , The function of exchanging register values can also be realized by using the following code , But it's obviously not as good as in always It is simple and intuitive to directly use non blocking assignment in blocks .

example

always @(posedge clk) begin
    temp    = a ;
    a       = b ;
    b       = temp ;
end