FPGA parsing B code----serial 1

前言

    现有：STM32已经编写好Bcode parser,Need to use nowFPGA解析B码.

    原因：CSDNCouldn't find it written onB码程序,Even if there are all to download,穷,There is no download point.

    区别：STM32是顺序执行,方便接收Bcode and parsingB码,同时有PWMAcquisition routine,定时器,计数器.

    难点：FPGA是并行结构,逻辑比较复杂.

写在前面

    之前使用FPGAJust write the serial port,SPI,doubleOperations on double-precision data.对于1sData and pulse width acquisitions have not been written yet,Now try to use your own summary of the writing method and standard writing step by stepBcode parser.

    写这篇文章的时候,I still don't know how to write it,The following step by step will show your way of thinking and procedures,希望能对学习FPGAFriends and analysisBCode friends to help,Save some time and money.也希望能和大家一起学习.

第一章：需求

    输入：B码;

    输出：1PPS信号,UTC时间,BCode key frame information.

第二章：B码结构

     信号时长：1s;

     信号种类：2ms：0电平（暗红色）;5ms：1电平（橙黄色）;8ms：Flag level（绿色）;

第三章：拆解

    Class dismantling：1PPS,Bcode information output;

    Small class dismantling：Pulse width acquisition,Symbol storage,时间计算,串口输出.

第四章：显示部分

    This part is best added,Show that your program is running,最好用1个LED灯进行显示,Then remove it after the final program is finalized,If there is a lot of space, then it is optional.

[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		timer <= 32'd0;                     
	else if (timer == 32'd9_999_999)    
    	timer <= 32'd0;                   
	else
		timer <= timer + 32'd1;            
end

        Come up with a counter first,General procedures use this format（This format is summed up by itself,方便,好看,简单,One by one,When you read it yourself, you can see what you wrote！）：

    （1）复位,变量赋值为0;

    （2）条件1,变量处理1;

    （3）条件2,变量处理2;

    （4）其他条件,变量处理3.

    Of course, other conditions can be added in between.Counter function from0加到9999999,然后再回到0.The specific maximum value is arbitrary.

    Then turn on the light again,to a certain value,flag加1,Then add it next time1,也就是flag在0和1之间变化.

[email protected](posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        flag <= 1'b0;
    else if(timer == 32'd8_999_999) 
        flag <= flag + 1'b1;
    else
        flag <= flag;
end
[email protected](posedge clk or negedge rst_n)
begin
    if(rst_n == 1'b0) 
	 begin
          led4<=1'b1;
    end
    else begin
    case (flag)
          1'b0   : led4<=1'b1;
          1'b1   : led4<=1'b0;
          default  : led4<=1'b0;
    endcase	
    end	 
end

    The structure is the same as before,复位置0,time的值等于8999999时flag加1,其他条件flag不变.

    Reset lights0,两个条件下LED分别置0和1,Represents on and off.

    这样LEDThe lights can be turned on and off according to a certain cycle.

第五章：Pulse width acquisition

    思路：I think this part is roughly divided into4部分,What exactly needs to be done,I'll have a look at programming！

    （1）上升沿检测;（2）下降沿检测;（3）The counter starts and stops after edge detection;（4）Pulse width time calculation.

    Rising edge detection and falling edge detection procedures：

//Pulse width rising and falling edge detection
reg        bpluse_en_d0; 
reg        bpluse_en_d1; 
wire       bpluse_falling_flag;
wire       bpluse_rasing_flag;
assign bpluse_falling_flag = (~bpluse_en_d0) & bpluse_en_d1;
assign bpluse_rasing_flag  = (~bpluse_en_d1) & bpluse_en_d0;
always @(posedge clk or negedge rst_n) begin         
    if (!rst_n) begin
        bpluse_en_d0 <= 1'b0;                                  
        bpluse_en_d1 <= 1'b0; 
    end                                                      
    else begin                                               
        bpluse_en_d0 <= bcodein;                               
        bpluse_en_d1 <= bpluse_en_d0;
        		  
    end
end

    When rising and falling edges are detected,两个flagA pulse signal of one cycle respectively.

//置位time是否开启
reg        timebeginflag; 
[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		timebeginflag <= 1'd0;                     
	else if (bpluse_rasing_flag == 1)      
    	timebeginflag <= 1'd1;                      
	else if (bpluse_falling_flag == 1)
		timebeginflag <= 1'd0; 
   else 
      timebeginflag <= 1'd0; 	
end

    when rising and falling,timebeginflag分别置1和0.

//The counter works after the rising edge,The counter stops after the falling edge
reg [31:0]      timer;
[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		timer <= 32'd0;                     
	else if (timebeginflag == 1)      
    	timer <= timer + 32'd1;                     
	else if (timebeginflag == 0)
		timer <= timer;             
end

    上升沿时,time计数器开始计数,下降沿时,time计数器停止.

    This piece is missing onetime复位为0的一个条件,这个条件为timeThe flag bit after the data in the counter is fetched,当取出time之后,time复位,Prepare for the next pulse width measurement.

    Pulse width calculator：

reg    bcodelevel; 
[email protected](posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		bcodelevel <= 0;                                        
	else if (bpluse_falling_flag == 1)begin
		if(timer >= 350000)bcodelevel = 3; //P电平
      else if(timer >= 200000)bcodelevel = 2; //1电平
		else if(timer >= 50000 )bcodelevel = 1; //0电平
		else bcodelevel = 0; 
   end
   else 
      bcodelevel <= 0; 	
end

    when the falling edge comes,time计数器停止计数,同时判断time中的数据,由于timedata is less accurate,The level after a wide range can be judged,大于7msis the flag level,大于4ms即为1电平,大于1ms即为0电平.中间用了else,所以3judgments do not conflict.In this way, the level of each pulse can be judged.

第六章：测试

    The program is written here first,Test the writing program tomorrow.The test program sends the corresponding directlymsnumber of level signals,Test whether the corresponding level can be collected.

    The overall idea is to collect the rising and falling edges first,启动计数器,The counter data size is judged at the falling edge,Output level type according to data size.Of course, the level has to be latched below,I can only think about it tomorrow