Introduction to SDC

Foreword

The related concepts are organized and summarized based on online data, and some of the content is quoted from the article after the text.

When writing the .sdc constraints file, the first thing to do is to use create_clock to constrain the clock entering the FPGA.Its syntax is as follows:

create_clock[-add] [-name ] -period [-waveform]

Parameter explanation:

-name indicates the name of the generated clock

-period represents the clock period in ns

-waveform can describe the clock duty cycle and its up and down position in detail

Port List

-add is used to add multiple clock constraints to a port

Example:

create_clock-period 10 -name clk_100 [get_ports clk]

A clock with a period of 10ns and a duty cycle of 50% is generated, its name is clk_100, and its port name is clk

create_clock-period 10 -waveform {8 12} -name clk [get_ports clk]

Generate a clock with a period of 10ns rising edge 8ns, falling edge 2ns

create_clock-period 10 -name clk_100 [get_ports clk]

create_clock-perioid 6.6 -name clk_150 -add [get_ports clk]

Generate two clocks on one port of clk with periods of 10ns and 6.6ns, respectively.If the same port in a system has multiple clock inputs at different times, the -add parameter can be used.Otherwise, if the -add parameter is not added, the clock defined later is invalid.

Note 1:

In Tcl syntax [] means command substitution, so [get_portsfpga_clk] will execute a command to find the port in the design that matches the name of fpga_clk.

Note 2:

Tcl and SDC are case sensitive, so make sure fpga_clk is exactly the same as the port name in the design

Reference

1. Author	Blog Post
	SDC timing constraints (1)-create_clock
	SDC files commonly used timing constraint statements
	SDC and TimeQuest API Reference Manual
	Tcl/Tk Beginner Classic
	TimeQuest User Guide