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Dspic33ep clock initialization program
2022-07-05 11:09:00 【Full stack programmer webmaster】
// file name p33clk.h
#ifndef _P33CLK_H_
#define _P33CLK_H_
//#include "p33clk.h"
#define WDT_ENB _SWDTEN = 1
#define WDT_DIS _SWDTEN = 0
// Clock source selection
#define OSCLK0 0 //FRC
#define OSCLK1 1 // belt PLL+N Frequency division FRC
#define OSCLK2 2 //HS MS LS The external clock
#define OSCLK3 3 // belt PLL Of HS MS LS The external clock
#define OSCLK4 4 // Retain
#define OSCLK5 5 //LPRC
#define OSCLK6 6 //FRC/16
#define OSCLK7 7 // belt N Frequency division FRC
// Processor and CPU Clock division ratio
#define DOZEDIV1 (0<<12)
#define DOZEDIV2 (1<<12)
#define DOZEDIV4 (2<<12)
#define DOZEDIV8 (3<<12)
#define DOZEDIV16 (4<<12)
#define DOZEDIV32 (5<<12)
#define DOZEDIV64 (6<<12)
#define DOZEDIV128 (7<<12)
//------------------------------
//Fosc = (Fin/V_FRCDIV/N1/N2)*M
#define V_FRCDIV V_FRCDIV1 //FRC Oscillation frequency division coefficient
#define V_N1 V_N1DIV(2) //x = 2--33 N1 Division coefficient
#define V_N2 V_N2DIV2 //N2 Division coefficient
#define V_PLLFBD PLLMF(50) //(x=2--513)PLL Octave ratio
//FRC Division coefficient
#define V_FRCDIV1 0
#define V_FRCDIV2 1
#define V_FRCDIV4 2
#define V_FRCDIV8 3
#define V_FRCDIV16 4
#define V_FRCDIV32 5
#define V_FRCDIV64 6
#define V_FRCDIV256 7
//N1
#define V_N1DIV(x) (x-2)
//N2
#define V_N2DIV2 0
#define V_N2DIV4 1
#define V_N2DIV8 3
//PLL Octave number M
#define PLLMF(x) (x-2)
//================================
extern void Init_Clk(uint16 OsClk) ;
#endif
// file name p33clk.c
#include "global.h"
#include "p33clk.h"
//***************************************
// The name of the function :InitClk
// The functionality : Initialize the clock
// Entrance parameters : Clock source selection FRC frequency division pll Octave ratio
// Export parameters : nothing
// Return value : nothing
// Fosc = (Fin/V_FRCDIV/N1/N2)*M
//***************************************
void Init_Clk(uint16 OsClk)
{
CLKDIV = 0X0000 ; // The clock ratio between processor and peripheral is 1:1
_FRCDIV = V_FRCDIV ; //FRC Division coefficient
_PLLPOST = V_N2 ;//N2
_PLLPRE = V_N1 ;//N1
PLLFBD = V_PLLFBD ;// PLL frequency doubling
OSCTUN = 0X0000 ; // Oscillator adjustment register Default 7.37M
REFOCON = 0X0000 ; // Reference clock = The system clock
OSCCON = 0X0000 ;
_OSWEN = 1 ; // The request for switching is made by NOSC Specified clock
_NOSC = OsClk ; // Switch New oscillator
while(_OSWEN) ;// Wait for the clock switch to complete
if((_NOSC == OSCLK1) ||(_NOSC == OSCLK3))// belt PLL
{
while(!_LOCK) ;// wait for PLL lock
}
REFOCON |= 0X8000 ; // Reference clock output enable
}
// Application example -- Clock initialization
//FRC The system clock 1 Frequency division to CPU PLL frequency doubling 50
//Fin = 7.37M Fcpu = Fosc/2 = 46.0625M
Init_Clk(OSCLK1) ;
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