Section 1: (3) logic chip process substrate selection

All logic chips use monocrystalline silicon substrates , Of course, the substrate requirements used in the advanced manufacturing process will also be higher . At present, the enterprises that monopolize the preparation of silicon substrates are mainly in Japan . The well-known business owners mainly include shinyue group in Japan （ Xinyue semiconductor ,Shin-Etsu）, Shenggao （Sumco）, Universal wafer in Taiwan , Germany's Siltronic And Korean LG silctron（SK siltron, Has been SK Acquisition ）, The domestic leading enterprise is Shanghai silicon industry .

In the past, Japanese and Korean substrates were mostly used in domestic factories , Now the silicon chips of domestic manufacturers have also come in , At least second source The best choice . The routine of advanced manufacturing process often uses the products of mature enterprises first , Do it after you succeed cost down, Take the cheap as second source Take the verification process and slowly replace . At present, advanced technology manufacturing is used 300mm The wafer , Xinyue semiconductor is the first to develop industrial 300mm Silicon wafers and currently available 11 individual 9 Purity of （ Purity requirements for electronic grade silicon 6 individual 9,99.9999%, Electronic grade high purity requirements 9 To 11 individual 9）, Its production technology and market share rank first in the industry . Of course, domestic manufacturers are also catching up , Shanghai silicon industry has been able to produce 14nm Monocrystalline silicon substrate for processing , More advanced ones are also under development . The general manager of Shanghai silicon industry is qiuciyun , So you see , Domestic semiconductor wafer enterprises with unlimited potential .

Some people wonder , How can the substrate be divided into different process nodes , Don't you do it all the same ？ This involves some specifications of the substrate . such as 28nm The most commonly used substrate is 300mm With light doping p Type epitaxial silicon (4um) Heavily doped monocrystalline silicon substrate , Its crystal plane index is （100）, The crystallographic index is <110>, The thickness is about 0.5mm, Of course, there are certain requirements for the defect density of states of the wafer .

We use Sumco Take the introduction of the company's official website as an example , You can see , The silicon wafer is cut and polished , There are also some special steps, such as annealing , extension , Isolated junction , The process of silicon on insulator can be further processed , This is to be screened for different applications , Let's introduce 28nm Epitaxial substrate used in logic process .

（1） Wafer size

You can see from the table in the figure , from 4 Inches to 12 Inch wafer , According to different application processes , Its size range is different . in general ,8 Inch wafer is still the most popular type in the semiconductor industry , But for advanced logic Manufacturing ,12 Inch wafer is already the industry standard . Of course, for larger diameter 18 Inch wafer voice , The industry has not yet formed an absolute consensus to industrialize . Larger wafer diameter can improve the utilization of monocrystalline silicon and reduce costs , But there will be higher requirements for monocrystalline silicon process （ Such as defects at the edge ）. What's more difficult is , This requires changes in the entire semiconductor industry , The main thing is that the equipment should be upgraded to 18 Inches match , At the same time, large-size wafers will also pose new challenges to various processes, such as wafer edge Some of side effect. Of course , Some organizations in the industry promote 18 Inch purpose , It is more about the surge in sales of various related interest chains brought about by forced upgrading and a new round of promotion to the industry , But at present, the biggest obstacle still comes from semiconductor equipment manufacturers .

（2） Doping type

The substrate of logic chip has p Type doping ,n Type doping , At present, most of them are p Type doping , The doped element is boron . Compared with n Type phosphorus doping , Boron is more conducive to the diffusion of the substrate . what's more , It will be useful in general circuit design native device, such device No additional light shield is required , Use parasitic MOS Tube is ok . The mobility of electrons is generally higher than that of holes 3 To 4 times , and p Parasitic on type substrate MOS The tube corresponds to NMOS. Familiar with the manufacturer WAT Our friends should know , There will be in the electrical parameters of each product Native NMOS and native IO NMOS Related parameters of , be relative to PMOS, these device There will be faster speed and driving ability .

（3） Surface epitaxy

28nm The substrates used are all epitaxial silicon , The thickness of this epitaxial silicon layer is about 4um, And the doping concentration is light . Compared with heavy doping inside the substrate , The resistivity of epitaxial silicon is often that of the substrate 100 More than times , The advantage of this high-quality silicon substrate is that it can be effectively improved CMOS Latch up effect caused by parasitic thyristors in the process . We all know SOI Silicon chip can completely eliminate the problem that the circuit triggered by thyristor cannot be closed , Epitaxial silicon is somewhat similar , Use the high resistance state to reduce the probability of triggering this effect , There are data indicating lightly doped p Type epitaxial silicon can improve 4-5 Times the latch up effect .

（4） Crystal plane index

MOS Tubes are surface channel devices , The density of states of defects on the substrate surface has a great influence on the threshold voltage , and （100） The surface atomic density of the crystal surface is the smallest , The corresponding atomic surface density of States is also the smallest , thus MOS The process uses （100） Substrate of crystal surface . in addition , because （100） The surface density of crystal plane is small , Its thermal oxidation and etching rates are also relatively fast , Of course, this factor is secondary .

（5） Crystallographic index

For crystal orientation , stay 40nm before ,CMOS Technology is often used <100> Crystallographic substrate . here we are 28nm, In order to maximize the improvement PMOS The mobility of , The industry has adopted <110> Crystallographic substrate . In this direction ,PMOS The channel is most sensitive to compressive stress , Therefore, the mobility can be improved to the greatest extent .28nm The process will use source drain SiGe stress technology to optimize hole mobility , stay <100> Crystal orientation , Can get about 20% The promotion of .

We can see from the first picture that the silicon wafer has a straight edge , The purpose of cutting this edge is to tell you how to determine the crystal orientation . The cut straight edge is generally called notch Direction .Notch When facing down ,poly It is generally vertical （28nm）. Of course, for those specially stipulated in the design rules or some IP modular , There will also be a level poly place . So-called <110> Crystal orientation , Actually means notch Horizontal direction when facing down , That is, the direction of the channel is <110>.

（6） Wafer thickness

The thickness of silicon wafer should be neither too thick nor too thin . Thick costs will rise , wasteful ; If it is thin, it may cause cracks in the process . There will be many metal layers superimposed in the later process , Finally, there will be two thick passivation layers , As the process goes on , The substrate will be subjected to accumulated stress, causing bending , If it is too thin , May cause substrate cracking . Even in better cases , The bending degree is too high , It will also lead to the existence of passivation layer and other thin films crack/peeling/edge defocus The risk of , Thus causing the final visual inspection and even the failure of reliability .

Of course , besides , stay foundary When selecting the substrate , Engineers can also request some special parameters , such as wafer edge leveling perhaps bevel Radian of ah, and so on , This can be selected according to some failure modes of the current process . however , If this is the case , There are indeed some serious problems that should not exist but recur in the process .

In the next section, we will briefly introduce online measurement （Inline Metrology）.