Understand chisel language thoroughly 06. Chisel Foundation (III) -- registers and counters

Chisel Basics （ 3、 ... and ）—— Registers and counters

Chisel In the last part of the foundation, we introduced Chisel Operators and combinatorial logic in , But to construct complex digital logic circuits , It is not enough to have combinational circuits , Because combinational circuits have no state information . This part introduces the basic components used to describe the state information of digital circuits , That's what we all know register （Register）. After introducing registers and operations on registers , We will implement a counter with registers .

register

Chisel Register components are provided in , The essence is D- trigger （D flip-flops） Set ,D- The concept of trigger belongs to the category of digital logic circuit , Don't start here , We can abstract it into registers .

Chisel The registers in are implicitly connected to the global clock , And on every clock The rising edge updates the register Value .

When providing an initialization value when declaring a register , Registers will use Synchronous reset The signal .

The value stored in the register can be any number that can be represented as a set of bits Chisel type , The following code defines a bit width of 8 The register of , It will be initialized to 0：

val reg = RegInit(0.U(8.W))

Enter the update operator := Connect to register , The output of the register can be directly referenced by the register name , Used in expressions ：

reg := d
val q = reg

The register circuit defined by the above three lines of code is shown in the following figure , Including a Implicit The clock signal of clock、 An initialization register is 0.U Implicit synchronous reset signal reset、 Input signal d And output signal q, Global signal global and reset Are implicitly connected to each register ：

Registers can also be used RegNext() To define , The parameters are its input and a constant as the initial value ：

val bothReg = RegNext(d, 0.U)

In order to distinguish between combinational logic and register signals when writing code , Usually, when naming, the register will be suffixed Reg. Another common method , Commonly used in Java and Scala, Is the use of camelCase（ Hump nomenclature ）, Use multiple words as identifiers . In this way , Functions and variables start with lowercase , And category （ type ）, For example, the module name , Just start with uppercase .

Chisel The naming in is relatively free , But it's best to use a good-looking and descriptive name . And it's important to note that ,Scala and Chisel Keywords in cannot be named . And about the Chisel Code specification of , I will write an article later .

Chisel Register and Mux Implementation counter

Counter is a very basic component in digital system , Such as performance counters 、 Program counter, etc . We may use registers to record the number of events , But more often it is used to define a time interval . That is, the counter records the number of clock cycles , When reaching a certain number （ After this time interval ） Trigger an action .

The simple method is to reset the counter when it reaches a certain upper limit . It should be noted that , Computer science and digital design , Counting is from 0 At the beginning , So if you want to count to 10, That's from 0 Count to 9.

The following code implements a counter , Count up to 9, Then start again 0 Count to 9：

val cntReg = RegInit(0.U(8.W))
cntReg := Mux(cntReg === 9.U, 0.U, cntReg + 1.U)

Yes, of course ,Chisel There are counters in the standard components Counter Of , We'll talk about that later ！

Although I say Chisel Will infer the required bit width for signals and registers , But it is better to specify the desired bit width when creating hardware objects . On most occasions , It is also best to give the register a known reset initialization value ：

val reg = RegInit(0.S(8.W))

If no initialization value is given , Let the register value be undefined at reset , It may save a reset loading network , But it will be much easier if the reset value is known during testing and verification .

Conclusion

There is not much about registers , But registers are modules with status information , It also implicitly introduces a clock , Therefore, it is the basis of sequential circuits . Then the combinational circuit has , Sequential circuits also exist , Theoretically, we can do whatever we want to achieve any digital circuit , It's also natural to implement a processor . In the next section, we will discuss Chisel Medium Bundle and Vec To introduce , This is the pit dug in the last section , These two structures can bring us a lot of convenience in writing code ！