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FPGA 学习笔记:Vivado 2019.1 工程创建
2022-07-03 19:33:00 【张世争】
前言
最近买了一块 【正点原子】达芬奇Pro FPGA开发板,学习下FPGA开发的相关知识
这个FPGA开发基于
Xilinx
的xc7a35tfgg484-2
,资源比较丰富Xilinx
如今推荐的开发IDE 是Vivado
,不再推荐使用ISE
,我使用Vivado 2019.1
,这个软件比较的庞大,占用约50~70G的硬盘
创建工程
创建工程这个部分,流程比较的简单,这里做个笔记
首先要安装好
Vivado 2019.1
,打开Vivado 2019.1
点击 【Create Project】创建一个新的Vivado 工程
给 Vivado 工程取个名字,注意不要使用中文目录、名字不含有空格、特殊符号
工程的类别,默认常用的:【RTL Project】,所以直接 【Next】即可
这里可以暂时不添加源文件,verilog HDL 的源文件,如
hello.v
,可以在创建工程后再加入,也可以选择【VHDL】语言选择 FPGA 的型号,这个需要选择实际的电路板上的FPGA 型号,我这个开发板是 :
xc7a35tfgg484-2
,在 【Search】搜索框里,可以输入 型号,筛选出想要的FPGA 的型号空的 Vivado FPGA 工程,就创建完成了
空工程如下,后面研究开发FPGA的整个流程
小结
这里先创建一个空的工程,发现就是一路的【Next】,选对 FPGA 型号即可,如果选的不对,后面可以更改
通过了解,Vivado 还支持 命令行,也就是
tcl
脚本的开发方式,这个后面再研究后面继续研究 源文件的添加、仿真、综合、实现、生成二进制文件,下载到板子上运行的流程
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