set_ case_ analysis

set_case_analysis Often used in many mode The design of the , Give some pin/port Set constant 0 or 1, To switch mode Analyze the function of time sequence . for instance , Exist in the design SCAN mode and FUNC mode, stay FUNC mode Lower bound SCAN enbale Signal use set_case_analysis Set to 0, stay FUNC mode I won't analyze scan clock The temporal .

set_case_analysis 0 [get_ports scan_enable]

In general ,set_case_analysis Act on MUX Selection signal of multiplexer , To achieve mode The choice of . Pictured 1.

create_clock [get_ports func_clk] -name func_clk -period 10 -waveform {0 5} 
create_clock [get_ports scan_clk] -name scan_clk -period 100 -waveform {0 50}

set_case_analysis 0 [get_ports scan_ena]

chart 1 

What is easy to trample on here is , Some front ends write sdc When you want to use set_case_analysis To switch the same mode Under the clock, But it doesn't consider whether it can be realized in the chip work , During the simulation, it is found that a certain clock is not long tree, Timing violations cannot converge . Pictured 2.sdc Set up set_case_analysis Give Way gen_clk Just choose func_clk -> FF1 -> MUX Along the way , but func_clk->FF2->MUX It also takes a long way tree. So this is set_case_analysis Setting is wrong .

create_clock [get_ports func_clk] -name func_clk -period 10 -waveform {0 5} 
create_generate_clock [get_pins FF1/Q] -name div2_clk -source [get_clock fumc_clk] -divide_by 2
create_generate_clock [get_pins MUX/O] -name div4_clk -source [get_clock func_clk] -divide_by 4

set_case_analysis 0 [get_pins MUX/S]

chart 2