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Makefile simple induction
2022-07-02 01:34:00 【CodeStarr】
List of articles
Official website :https://gcc.gnu.org/
file (7.4 edition ):https://gcc.gnu.org/onlinedocs/7.4.0/
Reference resources :https://seisman.github.io/how-to-write-makefile/overview.html
1. Basic use
# the first is the final target
main: main.c foo.o bar.o
gcc main.c foo.o bar.o -o main
foo.o: foo.c
gcc -c foo.c
bar.o: bar.c
gcc -c bar.c
explain : Final target document main Depend on main.c and func.o, from gcc Generate .func.c equally .
phony
phony False target .Makefile Of target The default is file , and phony The goal of is to execute the program .
Below demo Support make clearall
and make clear
Instructions .
CC = gcc
main: main.o
$(CC) main.o -o main
main.o: main.s
$(CC) -c main.s -o main.o
main.s: main.i
$(CC) -S main.i -o main.s
main.i: main.c
$(CC) -E main.c -o main.i
.phony: clean cleanall
clean:
rm main.i main.s main.o
cleanall:
rm main.i main.s main.o main
Multiple files can also be generated by using pseudo targets :
all : prog1 prog2 prog3
.PHONY : all
prog1 : prog1.o utils.o
cc -o prog1 prog1.o utils.o
prog2 : prog2.o
cc -o prog2 prog2.o
prog3 : prog3.o sort.o utils.o
cc -o prog3 prog3.o sort.o utils.o
The default target feature is , Always executed , But because of “all” Another false target , The pseudo target is just a tag and will not generate a file , So there won't be “all” Document generation
The rules
2. command
frequently-used echo command , Need to add @, So it doesn't show echo xxx
了 .
exception handling
If there is a command error ,make Will stop . But like mkdir This kind of order , Mistakes should continue , In this case, we can talk about a horizontal bar prefix :
-mkdir FOO
perhaps make -i
.
A semicolon
scene : The second command runs on the basis of the first instruction
cd /home/hchen; pwd
3. Variable
Specify compiler
If you don't use it one day gcc 了 , The above scripts have to be manually changed one by one . So you can save the compiler as a variable .
assignment :
- := Normal assignment ;
- = Recursive assignment ;
- += Additional assignment ;
- ?= Conditional assignment , The left side is undefined before assignment ;
CC := g++
main: main.c foo.o
$(CC) main.c foo.o -o main
foo.o: foo.c
$(CC) -c foo.c
Other parameters , Such parameters , The goal is , It is also often used as a variable .
CC := g++
TARGET := main
CFLAGS = -lm -Wall -g
$(TARGET): main.c
$(CC) $(CFLAGS) main.c -o main
Built-in variables
Makefile There are some very useful variables :
- [email protected], Target file ;
- $^, All dependent files
- $<, The first dependency file .
- $*, Target file without extension
- $?, Dependent files whose timestamp is later than the target file
CC := gcc
main: main.o
$(CC) $^ -o [email protected]
%.o: %.c
$(CC) -c $^ -o [email protected]
wildcard
# all .c
objects := $(wildcard *.c)
Target variable
It can be understood as a local variable , It only takes effect in the rules corresponding to the goal .
prog : CFLAGS = -g
prog : prog.o foo.o bar.o
$(CC) $(CFLAGS) prog.o foo.o bar.o
prog.o : prog.c
$(CC) $(CFLAGS) prog.c
foo.o : foo.c
$(CC) $(CFLAGS) foo.c
bar.o : bar.c
$(CC) $(CFLAGS) bar.c
4. grammar
Conditional statements
ifeq, ifneq
ifeq ($(CC),gcc)
libs=$(libs_for_gcc)
else
libs=$(normal_libs)
endif
ifdef
bar =
foo = $(bar)
ifdef foo
frobozz = yes
else
frobozz = no
endif
function
demo:
$(subst ee,EE,feet on the street)
5. Other
Some of the parameters
-f Appoint makefile
Compile subdirectories Makefile
subsystem1:
cd subdir && $(MAKE)
subsystem2:
$(MAKE) -C subdir
$(MAKE) It is a command line with parameters
Conflict situation
If there is main1.c and main2.c Each has one main, Just compile the first .
# perform
main1: main1.c func.o
gcc main1.c foo.o -o main1
# Don't execute
main2: main2.c func.o
gcc main2.c foo.o -o main2
# perform
func.o: func.c
gcc -c func.c
clean:
rm *.o main1 main2
Use all You can generate two .
all: main1 main2
main1: main1.c func.o
gcc main1.c foo.o -o main1
main2: main2.c func.o
gcc main2.c foo.o -o main2
func.o: func.c
gcc -c func.c
clean:
rm *.o main1 main2
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