Microcomputer principle - bus and its formation

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One 、 Bus definition and classification

Bus ： Is the channel for transmitting information , The practical application computer is divided into address bus 、 Data bus and control bus
classification ：① On chip bus ： The interior of an integrated circuit , Such as FPGA On chip bus is also a problem that users need to consider
② Component level bus （ In board ）
③ Internal bus ： Communication between circuit boards （ Also called system level bus ）
④ External bus ： Communication bus between devices
Both internal and external buses need to be standardized in design .

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Two 、 Introduction to several commonly used chips

2.1 74LS244（8 Bit data unidirectional buffer ）

LS： It means speed ;
74： Indicating temperature , It is a civilian device

2.2 74LS245（8 Bit data bidirectional buffer ）

Suitable for bidirectional bus buffer

2.3 74LS373（8 Bit latch ）

The truth table of chip usage is as follows ：

The first two cases are the follower , The third type is the latch .
374 The truth table of is ：

3、 ... and 、8086 Bus operation sequence

Instruction cycle —— The time required to execute an instruction , By several bus cycles （ Clock cycle ） form
Bus cycle —— It consists of several clock cycles
8086 The most basic bus cycle consists of 4 Clock cycles make up

3.1 Reset and start of the system

** keep 8086 Of reset The pins are maintained at least 4 A cycle can guarantee CPU Reliable reset .** High active ！
8086CPU After reset ,PSW DS ES SS IP And the instruction queue register are cleared ;
Segment register CS by FFFFH, So the physical address of the system startup is ：FFFF0H
So in general FFFF0H An unconditional jump instruction is stored in the starting unit , So as to move to the place where the system program actually starts .
8086 The reset operation sequence is shown in the figure below ：

3.2 Bus operation

8086CPU Minimum mode —— To external memory /IO The read / write control signal of is controlled by CPU The pins directly generate
8086CPU Maximum mode —— To external memory /IO The read / write control signal of is controlled by the bus controller 8288 Produced
Single processor systems generally operate in minimum mode , In multiprocessor systems 8086 Operating in maximum operating mode .
8086CPU Bus read cycle in minimum mode

DEN： Data valid signal
8086CPU Bus write cycle in minimum mode

8086CPU Bus read cycle in maximum mode

8086CPU Bus read cycle in maximum mode

8086 and 8088 The gap between

1.  From the inside ：
	a. 8086 The instruction queue register in is 6 Bytes of 
	b. 8088 The instruction queue register in is 4 Bytes of 
2.  Looking from the outside ：
	a. 8086 Yes 16 Data line 
	b. 8088 Yes 8 Data line 
	c. 8086 Pin M/¯IO  stay 8088 The pin in is IO/¯M
3.  During word alignment 
	a. 8086 It is divided into aligned and misaligned 
	b. 8088 There is no such distinction 

Why is odd address storage cycle longer ？

8086 Data types are divided into words （16 position ） And bytes （8 position ）
8086 The even memory of is the same as that of 8 Bits and bytes are connected , The height of the odd bank is the same 8 Bits and bytes are connected ;
And words are stored in odd addresses , But the low byte should be stored in the low address , High byte needs to be stored in high address , This is equivalent to the intersection between the address line and the storage medium , Data storage will use 2 Two bus cycles , Even address storage words do not have this problem .