PCIe Core Configuration

This section mainly introduces PCIe configuration under lattice diamond

1. First create a new project

Open the diamond software, select File-->New-->Project, and fill in the project name and project path in the pop-up dialog box

2. Select the device, the development board model LFE5UM5G-45F-8BG381IES

3. Select synplify pro for the synthesis tool.The lattice documentation requires PCIe IPcore to use synplify Pro as a synthesis tool

4. After the project is established, the project is an empty project at this time, open Clarity Designer.Check to create a new clarity Design, and fill in the design name. Do not select the Create a single sbx component option.I haven't figured out how to use this option yet.Otherwise, the PCIe IPcore will not be displayed later.

5. Select the Lattice IP Server in Clarity Designer, and double-click the IP option to pull data from the Lattice server, which requires networking.

6. After double-clicking, start downloading data

7. Expand the list and select PCIe

8. Right-click and select Install

9. Follow the prompts to select the installation path, and confirm to start the installation.After installation is complete.Double-click pcie, as shown below

10. Fill in the instance name in the pop-up pcie 5g endpoint, here we call it pcie_x1, click customize

11. In the pop-up PCIe configuration options, only simple modification.Most of them are kept by default, because most of the options are not yet fully understood.Select Enable BAR0 in configuration space-1, fill in FFFFF000, continue to scroll to the bottom, and check Load IDs from ports.As shown below

Note: FFFFF000 of bar0: indicates the space attribute

bit0: 1'b0: Mem space 1'b1: IO space

bit[2:1] : 2'b00: 32-bit mem space 2'b10: 64-bit mem space

bit3: mem space prefetch bit.1'b0: non-prefetch 1'b1: prefetch

bit[31:4]: Space size.32'hFFFFF000: Indicates the space size 0xFFF, which is 4KBytes

The size of the space read by the host computer is to read the value of bar0 and the number of binary 0s from the lower digit (the lower 4 digits are 0 by default)

The Load IDs option is to put the manufacturer, device and other IDs on the instantiated port, and directly pass the value when calling IPcore

After clicking configure, click the close button, and the synthesizer starts to generate PCIe IPcore.It takes a few minutes to generate the IPcore.Wait for the build to complete.Then close Clarity Designer and save it, then pcie_x1.sbx will be added to the project.

12. Double-click the sbx file, reopen the clarity designer, add the clock module, select the extref module as shown below and fill in the example name

13. Select configure in the pop-up dialog box, then select close to close the dialog box, and wait for the synthesis tool to generate the reference clock IPcore

14. After IPcore is generated, open the Planner tab to see

15. Zoom in on the DCU area in the lower right corner of the above figure. Enlargement method: hold down the ctrl button, scroll the middle mouse button, drag extref to the extref area of ​​the dcu, drag Lane0 to the ch0 area of ​​the DCU.Drag and drop method: hold down the left button of the mouse and move.

16. After the drag is correct, double-click the Ch0 area to pop up the DCU settings, set the reference clock to DCU0_EXTREF. Then click the OK button

17. At this point, the PCIe IPcore configuration steps are completed, then start to generate IPcore, click the save button, and then click Generate to generate IPcore

Wait a few minutes for the PCIe IPcore configuration to complete.Afterwards, the pcie.v file and the instantiated template will be generated in the project directory

In the next section, analyze the pcie.v file