CPU design practice - Chapter 4 practice task 3 use pre delivery technology to solve conflicts caused by related issues

Preface

Practice task three is in Practical task 2 On the basis of the above ！！！
stay lab4 In an experimental environment , Add the corresponding code and use the pre delivery technology to solve the conflicts caused by related , Finally, the simulation time is less than that of practical task two .

experiment

1. Add the execution level 、 The data of memory access level or write back level is delivered to the data path of decoding level

At the decoding level, it is judged that the current time is at the execution level 、 Whether the register number of the destination operand of the memory access level or write back level instruction is the same as that of the source operand of the decoding level , Indicates that data correlation has occurred , The execution level 、 The data of the memory access level or write back level is delivered to the decoding level . The code is as follows ：

EXE_stage:		
	output [31:0] EXE_result,    // Executive level 
	assign EXE_result      = es_alu_result;
	
MEM_stage:	
	output [31:0] MEM_result
	assign MEM_result      = ms_final_result;
	
WB_stage:		
	output [31:0] WB_result
	assign WB_result         = ws_final_result;
	
ID_stage：
	input  [31:0] EXE_result,
	input  [31:0] MEM_result,
	input  [31:0] WB_result,

stay mycpu_top Add the corresponding signal to the instantiation of the corresponding module ：

// Instantiate the line declaration used 
	wire [31:0] EXE_result;
	wire [31:0] MEM_result;
	wire [31:0] WB_result;
	
ID_stage:
    .EXE_result     (EXE_result), 
    .MEM_result     (MEM_result),
    .WB_result        (WB_result)
    
EXE_stage:
	.EXE_result     (EXE_result)
	
MEM_stage:
    .MEM_result     (MEM_result)
    
 WB_stage:
    .WB_result        (WB_result)

2. It is the execution level that needs to be delivered before judgment 、 Data at the access level or write back level

At the decoding level, we get that the current time is at the execution level 、 The instructions of memory access level and write back level need to be finally written back to the destination operand of the register , Next, we need to generate corresponding logic to judge that what needs to be passed forward is the execution level 、 Data at the access level or write back level . The code modified at the decoding level is as follows ：

// Delete 
/* assign rs_value = rf_rdata1; assign rt_value = rf_rdata2; */

// add to -begin
assign rs_value = rs_wait ? (rs == EXE_dest ?  EXE_result :
                             rs == MEM_dest ?  MEM_result : WB_result)
                            : rf_rdata1;
assign rt_value = rt_wait ? (rt == EXE_dest ?  EXE_result :
                             rt == MEM_dest ?  MEM_result : WB_result)
                            : rf_rdata2;

assign ds_ready_go    = ds_valid & ~load_stall;  
//load_stall In practice, task 2 has been added , It means the first one i The first instruction is load Instructions , The first i+1 Orders 
// and load Instruction occurrence data correlation , At this time, the data that needs to be delivered in advance is not ready , Pipeline pause required .
// add to -end

experimental result

 Simulation results ：
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 958.809 ; gain = 0.000

 Tested ：
----PASS!!!
run: Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 958.809 ; gain = 0.000