Proteus simulation of buck switching power supply based on 51 single chip microcomputer

BUCK Topology output section

Here is the reference circuit given （ Here's the picture ） Two routes were used L293D Output OUT1 and OUT2, Then you will be very confused ....

1. About two routes L293D The output of ？

Because when the program is controlled ,IN2 It is always output by the single chip microcomputer 0, So it doesn't look like difference , It's hard to understand why .
The ideal state ： When out1 =1, The diode is not conducting , Upper inductive charging , Charge the lower inductor through the load , At low level, the inductance goes up along the diode , Afterflow . But the reality is that there are several issues to consider ：

• （1） When L293D Input is 0 When ,OUT2 yes 0, It is not a high resistance state
  So follow L293D, Single chip microcomputer IO The port will bear a large current , In this case , It's easy to burn the circuit , The direct current in this circuit finally flows from OUT2 I'm out , There is no diode for freewheeling , Instead, the diode is a little redundant ...
  Because of the previous BUCK Because of the front mos Completely cut off , There is no circuit , Diode is needed , But if you use OUT2, Always low , Not really

• （2） If you go the other way L293D, Let its output be in high resistance state , Not good either. , Because the capacitor at the bottom blocks the DC , Unable to flow into ,（ You can't say , Take off the capacitor , Otherwise, what is the meaning of adding the following inductor ？） and OUT2 Also high resistance state , There is no direct return path , There is no way to work .

• （3） When OUT1 Also for the low time , Actually, it is shown in the figure below , because OUT2= 0, So because L2 Positive on the left , Negative on the right , So actually L2 Negative voltage on the right side of ,L1 The right side of the is a positive voltage , He depends on L1 The positive voltage of L2 The output voltage is obtained by such a voltage difference of the negative voltage of ., The key is , A negative voltage is present in the circuit , Strange .
  
• (4) Okay , If both circuits output PWM, In this case , The upper and lower outputs different duty ratios , Make a difference , In this case , In theory , And the ripple will be small , But it will be difficult to control , Unable to strictly control MOS Whatever we want PWM switch , It will inevitably lead to two MOS Strange phenomenon of simultaneous conduction , Therefore, it is necessary to design a dead zone with sufficient length and width , Let two MOS It is impossible to conduct at the same time , Therefore, a special controller is generally required .（ forehead , After a look, it seems that it is not synchronized mos, After all, it is always on .....）

2. Output voltage and ADC Sampling voltage problem

The following figure VA It's the output voltage ,VB It should be ripple ,VC yes ADC Sampling voltage ,VC = VB + VA,,

• （1）IN0 Voltage problem ： IN0 The voltage of is the voltage obtained from the ground , Contains the voltage across the capacitor , That is to say, the voltage measured by the voltmeter is at both ends of the resistance , But the label is not . This leads to ADC Sampling value error , Unable to get the correct feedback voltage , The output voltage is not correct
  
  Therefore need Change my ADC The reference voltage of ,
  It's a little better after the change
  

• （2） If the output is IN0, But it is better to use the sampling network for sampling , The adjustment range is larger . because ADC Maximum reference voltage
  
  So this can increase the sampling range . If you use output directly , Then you can only output 5V It's at the top .

3. Load resistance and voltage divider network

Now the voltage divider is the load ,, But the normal load can be divided into two ？
It must be a whole load ,,,, The voltage dividing resistors are all feedback loops, and large resistors can be used to divide the voltage , The capacitance gets very little , The load is good , The load is well grounded

I increased the resistance sampling resistance 1000 times , There is no voltage on the capacitor . Before, the capacitor was divided into voltage because , AC current in the circuit , The resistance is not very large , From the vector method , Capacitive partial voltage . Here's the picture ,10 The ohm is no longer connected to the circuit between the two outputs , Direct ground . But in that case , The branch road below is useless .

In fact, whether the voltage ripple on the capacitor is also worth discussing , classical buck yes , But the capacitor is connected in parallel with the load , But here it is connected in series with the voltage dividing network first , Connect another load in parallel , It's strange , The whole journey was strange ......

4. SCM interrupt time problem

TF In case of overflow, it is set by the hardware 1, It is automatically cleared by the hardware after entering the interrupt service program 0 , That is to say, entering the moment of clarity 0 .
If timing 1us Enter an interrupt , In fact, it is a random intrusion that has been interrupted all the time , in other words , But it's strange ,LCD Show that the function is still running normally ,,,emmm