Ram of IP core

RAM IP Introduction to nuclear

RAM It's random access memory （Random Access Memory） For short , It's a volatile memory .RAM When working, you can write or read data from any designated address at any time , At the same time, we can modify the stored data , That is, write new data , This is a ROM Functions that you don't have .

Altera To launch the RAM IP There are two types of nuclei ： Single port RAM And dual port RAM.

RAM It is also divided into simple dual ports RAM And true dual port RAM：

• Single port RAM, Read and write operations share a set of address lines , Read and write operations cannot be performed at the same time
• Simple dual port RAM, Read and write operations have dedicated address ports （ A read port and a write port ）, That is, the write port can only write but not read , The read port can only read but not write
• True dual port RAM, There are two address ports for read and write operations （ Two reads / Write the port ）, That is, both ports can enter
  Line reading and writing .
   

Single port RAM Interface signal

Simple dual port RAM Interface signal

  True dual port RAM Interface signal

RAM IP Nuclear configuration

Single port RAM Configuration of

The second picture is to choose whether to create “aclr” Asynchronous reset signal and whether to create “rden” Read enable signal , You can check according to the actual design requirements , Here we check them all . Back EDA、Summary Are all the same .

The following figure shows the data output type of reading an address when it is about to be written data ： Yes Don’t Care（ No concern ）、 New Data（ New data written ） and Old Data（ Original data ）, We keep the default New Data that will do , in other words , When an address will be written to new data , Reading at the same time will read out new data

Simple double mouth RAM Configuration of

The first line is simple double port RAM, The second line is real double mouth RAM, Here we choose simple double port RAM Explain to you . The third line is setting ROM The way of memory size ,“As a number of words” It is determined by the number of words ,“AS a number of bits” It is determined by the number of bits . By default, we choose to determine by the number of words .

 

  True dual port RAM Configuration of

RAM IP Nuclear use

Press the button 1 In time RAM Address 0~255 Write data in 0~255; Press the button 2 When reading RAM The data in , From address 0 Start every 0.2s Address to add 1 Read down ; Press the key again 1 Stop reading and rewrite data when 0~255; Press the key again 2 Read data from the beginning .

 RAM Control module

  When you press the button 1 when （key1_flag=1） Explain to start going RAM The data is written in .RAM The writing sequence of is ： When RAM The rising edge of the write clock is taken until the write enable is high , The data acquired by the rising edge can be written into the address acquired by the rising edge . So want to go RAM There must be a clock to write data in , Write enable , Address , Write data signal .

wr_en： Write RAM Enable signal , Highly effective , Only when it is high can it go RAM Write the data . So when a key is detected 1 When the dithering signal is valid , We pull up the write enable , Start to go RAM Write the data .

addr： When the write enable signal is high , We need to write RAM To write data to the address . Here we are from 0 The address begins to write , Write an address on the rising edge of a clock , Write to the last address in turn 255. When the last address is written, pull down the write enable signal , Stop writing .

wr_data： write in RAM The data of . When both enable and address signals are available , Add the address and you can go RAM Data is written in . Here we can make the data equal to the address . That is, write data to the address 0~255.

The timing of read and write operations is the same . Are triggered by the rising edge of the clock .RAM The reading sequence of is ： When RAM The rising edge of the reading clock is taken until the reading enable is high , The data in the address collected by the rising edge can be read . If we configure IP When the core is not generated RAM Reading enable , that RAM The data in the address collected by the rising edge of the reading clock can be read directly .

rd_en： read RAM Enable signal , Highly effective , Only when it is high can it be read RAM The data in . When a key is detected 2 When the dithering signal is valid , We pull up the read enable signal , Start reading RAM The data in . Because the data we read out should be displayed on the nixie tube , If you read too fast , We can't see it with our naked eyes . So here we design every 0.2s Read an address . In this way, we can clearly see the data we read

When 0.2s After the counter is generated , Every time we detect that the counter reaches the maximum value, we will add one to the address , So we can every 0.2s Read out in turn RAM The data in . When the data of the last address is read , Let's return the address to 0 Restart reading , In turn, cycle .

If we are going RAM When you write data in the computer , Press the button 2（ Read button ） Will not read RAM The data in , Press the key when the write enable is low 2（ Read button ） Will pull up the reading enable . If we are going RAM When you write data in the computer , Press the button 1（ Write key ）, Then we will return the address to 0, from 0 Address begins to be rewritten .

RAM Control module reference code (ram_ctrl.v)

module ram_ctrl
(
   input        wire           sys_clk,
   input        wire           sys_rst_n,
   input        wire           wr_flag,
   input        wire           rd_flag,
                               
   output       reg            wr_en,     // Output write  RAM  Can make , High point level is effective 
   output       reg  [7:0]     addr,      // Output read / write  RAM  Address 
   output       wire  [7:0]    wr_data,   // Output write  RAM  Can make , High point level is effective 
   output       reg            rd_en      // Output read  RAM  Can make , High active 
);

parameter   CNT_MAX =24'd9_999_999;

reg     [23:0]   cnt_200ms;

[email protected](posedge sys_clk or negedge sys_rst_n)
       if(sys_rst_n == 1'b0)
	      cnt_200ms  <= 24'd0;
	   else if((cnt_200ms == CNT_MAX) || (wr_flag == 1'b1) || (rd_flag == 1'b1))
	      cnt_200ms  <= 24'd0;
	   else if(rd_en == 1'b1)
	      cnt_200ms  <= cnt_200ms + 1'b1;

//wr_en: Generate write  RAM  Enable signal 	   
[email protected](posedge sys_clk or negedge sys_rst_n)
     if(sys_rst_n == 1'b0)
	      wr_en  <= 1'b0;
	 else if(addr == 8'd255)
	      wr_en  <= 1'b0;
	 else if(wr_flag == 1'b1)
	      wr_en  <= 1'b1;

// When write enable is effective ,
[email protected](posedge sys_clk or negedge sys_rst_n)
     if(sys_rst_n == 1'b0)
	      addr   <= 8'd0;
     else if((addr == 8'd255&&wr_en == 1'b1) || (addr == 8'd255&&cnt_200ms == CNT_MAX)
	 || (wr_flag == 1'b1) || (rd_flag == 1'b1))
	      addr   <= 8'd0;
	 else if((wr_en == 1'b1) || (rd_en ==1'b1 && cnt_200ms == CNT_MAX))
	      addr   <= addr + 1'b1;

// Make the written data equal to the number of addresses , That is, write data  0~255		  
assign wr_data = (wr_en == 1'b1) ? addr : 8'd0;

//rd_en: Generative reading  RAM  Enable signal 
[email protected](posedge sys_clk or negedge sys_rst_n)
       if(sys_rst_n == 1'b0)
	      rd_en  <= 1'b0;
	   else if(wr_flag == 1'b1)
	      rd_en  <= 1'b0;
	   else if(rd_flag == 1'b1 && wr_en == 1'b0)
	      rd_en  <= 1'b1;
	   else
	      rd_en  <= rd_en;

endmodule

 RAM Top level code module reference code (ram.v)

module  ram
(
   input  wire         sys_clk,
   input  wire         sys_rst_n,
   input  wire         wr_key,
   input  wire         rd_key,
   
   output wire         ds,
   output wire         oe,
   output wire         shcp,
   output wire         stcp
);

wire           wr_flag;
wire           rd_flag;
wire           wr_en  ;
wire    [7:0]  addr   ;
wire    [7:0]  wr_data;
wire           rd_en  ;
wire    [7:0]  out_data;

key_filter
#(
    .CNT_MAX  (20'd999_999)
)
key_filter_wr_inst
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .key_in   (wr_key),
  
   .key_flag (wr_flag)
);

key_filter
#(
    .CNT_MAX  (20'd999_999)
)
key_filter_rd_inst
(
   .sys_clk  (sys_clk),
   .sys_rst_n(sys_rst_n),
   .key_in   (rd_key),
  
   .key_flag (rd_flag)
);

ram_ctrl   ram_ctrl_inst
(
   .sys_clk  (sys_clk  ),
   .sys_rst_n(sys_rst_n),
   .wr_flag  (wr_flag  ),
   .rd_flag  (rd_flag  ),
   
   .wr_en    (wr_en  ),
   .addr     (addr   ),
   .wr_data  (wr_data),
   .rd_en    (rd_en  )
);

ram_8x256_one	ram_8x256_one_inst 
(
	.aclr     ( ~sys_rst_n ),
	.address  ( addr ),
	.clock    ( sys_clk ),
	.data     ( wr_data ),
	.rden     ( rd_en ),
	.wren     ( wr_en ),
	.q        ( out_data )
);

seg_595_dynamic   seg_595_dynamic_inst
(
   .sys_clk  (sys_clk          ),
   .sys_rst_n(sys_rst_n        ),
   .data     ({12'b0,out_data} ),
   .point    (6'b000_000       ),
   .sign     (1'b0             ),
   .seg_en   (1'b1             ),
  
   .ds       (ds  ),
   .oe       (oe  ),
   .shcp     (shcp),
   .stcp     (stcp)
);


endmodule

RTL View

 RAM IP Nuclear simulation

`timescale   1ns/1ns
module   tb_ram();

reg          sys_clk;
reg          sys_rst_n;
reg          wr_key;
reg          rd_key;

wire         ds     ;
wire         oe     ;
wire         shcp   ;
wire         stcp   ;

initial
     begin
	    sys_clk = 1'b1;
		sys_rst_n  <= 1'b0;
		wr_key = 1'b1;
		rd_key = 1'b1;
		#20
		sys_rst_n  <= 1'b1;
		#10000
//rd_key		
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#200
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#200000
//wr_key		
		#20
		wr_key =1'b1;
		#20
		wr_key =1'b0;
		#20
		wr_key =1'b1;
		#20
		wr_key =1'b0;
		#200
		wr_key =1'b1;
		#20
		wr_key =1'b0;
		#20
		wr_key =1'b1;
		#20
		wr_key =1'b0;
		#20
		wr_key =1'b1;
		#10000	
//rd_key		
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#200
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#200000	
//rd_key		
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#200
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
		#20
		rd_key =1'b0;
		#20
		rd_key =1'b1;
	 end
	 
//sys_clk: Analog system clock , Every time  10ns  The level is reversed once , The period is  20ns, The frequency is  50MHz
always  #10  sys_clk = ~sys_clk;

// Redefine parameter values , Shorten the simulation time 
defparam    ram_inst.key_filter_wr_inst.CNT_MAX = 9;
defparam    ram_inst.key_filter_rd_inst.CNT_MAX = 9;
defparam    ram_inst.ram_ctrl_inst.CNT_MAX = 99;

ram   ram_inst
(
   .sys_clk  (sys_clk  ),
   .sys_rst_n(sys_rst_n),
   .wr_key   (wr_key   ),
   .rd_key   (rd_key   ),
   
   .ds       (ds  ),
   .oe       (oe  ),
   .shcp     (shcp),
   .stcp     (stcp)
);

endmodule