Verilog daily question (simple implementation of VL30 RAM)

Title Description ：

Achieve one Depth is 256, The seat width is 4bit Dual port RAM, All data are initialized to 0000. There are two sets of ports , Used for reading data and writing data respectively , Read and write operations can be performed simultaneously . When reading data indication signal read_en Is valid , By reading the address signal read_addr Read the data in the corresponding position read_data, And the output ; When writing data indication signal write_en Is valid , By writing the address signal write_addr And write data write-data, Write the corresponding data to the corresponding position .

The signal interface diagram of the program is as follows ：

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,  // Address width log2(256)-1 = 7.
	output reg [3:0]read_data
);
    
	// Write data , Depth is 256, Storable 2^8=256 Data , Declaration array array
    reg [3:0] array [255:0];
    integer i;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            for(i=0;i<=255;i=i+1)
                array[i] = 0; // Set all zeros 
        end
        else 
            array[write_addr] =(write_en)? write_data:array[write_addr]; 
        // According to the energy signal write_en, To declare the input address and data （ My understanding is to define a pointer ）
    end
    
    // Read it ,
    reg [3:0] data;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) read_data = 0; // Asynchronous zeroing 
        else read_data =(read_en)? array[read_addr]:read_data;
        // The enable signal is 1 Read only when 
    end
   
endmodule

// I'd like to review counting electricity when I'm free RAM Details of this part