[DSP] [Part 2] understand c6678 and create project

2022 year 6 month 16 Japan

1. TMS320C6678

• The letters here C Express CMOS process .
• C66x The core of the series .C6655 Single core ,C6657 Dual core ,C6678 Eight cores .
• use KeyStone framework .
• 4 road SRIO.
• High power consumption , Cooling fins and fans are required for operation .

1.1 KeyStone framework

1.1.1 Memory Subsystem Memory subsystem

（1）64 position DDR3,EMIF

• EMIF yes External Memory Interface For short , convenient DSP and FPGA A lot of data exchange between .
• DDR, Indicates double data rate SDRAM.
  （2）MSMC,The Multicore Shared Memory Controller
• MSMC,4MB,MSM,SRAM.
• Multi core shared memory controller (MSMC) management Multiple in multi-core devices TMS320C66x CorePacs、DMA、 Other master peripherals and EMIF Between Traffic （manage traffic）.
• MSMC It also provides a shared On film SRAM, Available for all C66x CorePacs And the master peripherals on the device .
• MSMC To access from the system host MSMC SRAM and DDR3 Memory Provide memory protection .
• C6678 Of MSMC Be responsible for handling all master（ Include 8 A nuclear , as well as SMS and SES Interface ） Yes MSMC SRAM and DDR3 Access requests for .

1.2 BootRom

• adopt TeraNet Bus , You can visit BootRom.
• Address range ：0x20B00000-0x20B1FFFF,128KB.
• DSP Use BootRom, It can support a variety of startup processes .
• ROM Bootloader (RBL) Use a set of Parameter table To perform the boot process . BootRom from I2C EEPROM（ Or from SPI equipment ） Read from Parameter table , Each parameter table is 0x80 byte .
• The parameter table is divided into general part parameters and special part parameters .

1.2.1 Start parameter table - General part

1.2.2 Start parameter table - Special part

1.2.2.1 EMIF16 Start mode parameter table

1.2.2.2 SRIO Start mode parameter table

1.2.2.3 Ethernet Start mode parameter table

1.2.2.4 PCIe Start mode parameter table

1.2.2.5 I2C Start mode parameter table

1.2.2.5 SPI Start mode parameter table

1.2.2.5 HyperLink Start mode parameter table

• A little

1.2.3 Start completion register

• Boot Complete Register.BOOTCOMPLETE Register control BOOTCOMPLETE Pin status . The purpose is to indicate ROM The completion of the guidance process .
• In register Bit0-7, Used to indicate the kernel 0-7 Whether the startup status of is completed .
• BootROM The code will be implemented , So that each kernel immediately sets its corresponding... Before jumping to a predefined location in memory BCx position
  

1.3 Semaphore Semaphore

• The device includes an enhanced semaphore module , Used to manage DSP C66x CorePacs Shared resources .
• Semaphore memory address ：0x02640000-026407FF , 2K The size .
• Semaphore force For shared Chip level resources Conduct （ nucleus ） visit , So as not to destroy the reading - modify - Write sequence .
• The signal gauge block has a unique interrupt for each kernel , To identify when the kernel gets resources .
• The semaphore resources in the module do not depend on specific hardware resources .
• Semaphore module supports 8 Host computer , contain 32 A semaphore （ Used in the system ）.
• Semaphore modules can only be used by privileged ID (privID) 0 To 7 Main device access , This means that only CorePac 0 To 7 or CorePac 0 To 7 Sponsored EDMA Transactions can access semaphore modules .

1.4 EDMA

• Enhanced Edition DMA, Enhanced Direct Memory Access (EDMA3) Controller.
• EDMA3 The main purpose of is to map two memories on the device From the endpoint Provide services for user programmed data transmission between .

1.4.1 Three EDMA Channel controller

• （C6678 DSP）EDMA3CC0, EDMA3CC1, and EDMA3CC2.

1.4.1.1 EDMA3CC0

• EDMA3CC0 Channel controller , There are two transmission controllers EDMA3TC1,EDMA3TC2.

1.4.1.1 EDMA3CC1

• EDMA3CC1 Channel controller , There are two transmission controllers EDMA3TC0,EDMA3TC1,EDMA3TC2,EDMA3TC3.

1.4.1.1 EDMA3CC2

• EDMA3CC2 Channel controller , There are two transmission controllers EDMA3TC0,EDMA3TC1,EDMA3TC2,EDMA3TC3.

1.5 Power management

• PowerManagement

1.5.1 Power status control register

• Power State Control Register (PWRSTATECTL) Controlled by software , To indicate the power saving mode .
• ROM The code reads this register , To distinguish various power saving modes .
• This register consists only of POR eliminate , And will continue to exist after all other devices are reset .
  

1.5.2 Power down control

• Power-Down Control
• C66x CorePac Support for closing C66x CorePac Power supply of each part .
• C66x CorePac Power off controller (PDC) Can be used to close L1P、 Cache control hardware 、DSP And the whole C66x CorePac.
• C6678 Currently not supported L2 Power down mode of memory .
• These power-off functions can be used to design the system to reduce the overall system power requirements .

1.5.3 Power Supply

• Power Supplies,
• We need to pay attention to , How to start correctly C6678 Correct power sequencing and timing required .

1.5.3.1 What are the power supplies

1.5.3.2 Power on sequence

• Power-Supply Sequencing
• The device has two acceptable power sequences . The following is a brief introduction , To be analyzed in detail later .

（1） The first sequence stipulates , The core voltage starts stay IO Before voltage , As shown below ：

1. CVDD 
2. CVDD1, VDDT1-2
3. DVDD18, AVDD1, AVDD2
4. DVDD15, VDDR1-4

（2） The second sequence is provided with other TI Processor compatibility , Its IO The voltage starts before the core voltage , As shown below ：

1. DVDD18, AVDD1, AVDD2
2. CVDD 
3. CVDD1, VDDT1-2
4. DVDD15, VDDR1-4

1.6 PLL

• Three pieces of locking phase ring ,PLL
• PLL The default setting is set by BOOTMODE[12:10] Bit decided .

2. GPIO

• Hardware initialization , When not configured ,GPIO Working on the dominant frequency 6 frequency division .
• Pin reuse configuration （ If there is reuse, carry out this operation ）.
• To configure GPIO The port is output
• To configure GPIO Port output high level

2.1 GPIO peripherals

• Universal I / O port .
• Peripheral clock （CPU/6）. The specific working frequency of the pin is slower than this ,CPU Control and EDMA control The bus path is different . Use EDMA It's going to be a lot faster .

2.1.1 EDMA

• EDMA Events and interruptions
• GPIO Events GPINTn Will be output to EDMA And interrupt （CPU）.

2.1.2 GPIO Event level

• There are primary and secondary events （ We need to arrive first. CIC And then the interruption ）

2.1.3 GPIO Binding and sharing with multi-core

• GPIO Corresponding relationship between port and core serial number , Binding relationship （local）, Shared by multiple cores （share）.

2.1.2 MMR Memory mapped registers

• 32 Bit address significant bit ,36 Bit address line .
• Control of peripherals , That is, access to memory address, read and write .
  《6678-datasheet-2014》
  
  《General Purpose Input/Output (GPIO) for KeyStone Devices User Guide》
  

3. Create a project

• With CCSv5 For example .
• Learning video ： A dragon

3.1 Create workspace WorkSpace

• Note that the file path can only contain ACII Code character （ Can't speak Chinese and so on ）.
  

3.2 Create project Project

• Get into CCS Edit Perspective interface

3.2.1 New project

3.2.1 Write code

• As can be seen from the above ：
  GPIO The base address ：0x02320000,DIR Register offset address ：0x10 ,OUT_DATA Register offset address ：0x14 .
• C6655,C6657 Development board ,LED Pin reuse exists in pin , Pin remapping required , Need to unlock kick.
  
• C6678 There is no pin reuse on , No need to turn on kick. And 3 individual LED There are differences in control logic , Hardware upper backplane led It needs to be set low to light led, The core board is raised and lit .
  

3.2.1 To write CMD file

• There must be some documents . File extension “.cmd”.
• The main function , Know memory allocation , It works in the linking process , Modify some link options .
• There are mainly two parts , One is the description of the memory area （ If you need to put it in that memory space, write it on which side , It's OK to write more ）, One is segment allocation .
  

3.2.4 Set stack size , Heap size

• Engineering setup
  
• Or directly at cmd Add... To the file （C6655 and C6678 The size of shared memory space is different ）
  

3.2.5 debug Under the map file

• View the detailed space information after compilation .

4. Download to board , debug

• Method 1 ： Debugging tools （ Emulator ）.XDX100 series （10KB Buffer data ）,200 series （100KB Buffer data ）,560 series （1MB Buffer data ）. Tracking function .
• Method 2 ： The written program conversion can start the image format , Burn and download to DSP Of CPU It's external FLASH in （EEPROM,NorFLASH,NANDFLASH wait ）.（C6000,DSP There is no film FLASH）
• Reference video ： A dragon

4.1 Create an emulator configuration file

• File-new-target configuration file
• Emulator configuration file , It only matters when debugging , Not a necessary document for a project .
• Emulator configuration file , You can create for the current project , You can also create a shared global emulator configuration file , Easy to use . All projects can use this configuration file .
  
• Or open a window , newly build target configuration file.
  

4.1.1 Create a global emulator configuration file

• Give a file name .
• Storage location , Choose a shared path .
  
• Choose a good simulator model
• Choose the device model
• Click save save
• If you choose some development board models , The emulator configuration file will load one by default GEL file .
  
• Click on target Configuration（ Or below Advanced）, Advanced configuration .
• Choose the core C66x_0. Other cores can also be selected , But choose something else , Generally, you will not call . Just at the core 0 Load the initialization file GEL That's all right. .
• Select initialization script on the right , Click on Browse Browse . Find the corresponding GEL file .
• GEL Only in the file CCS Effective when debugging the environment . It is completely independent of the user's program , Its function is only for debugging , Complete some initialization for us （ Configure clock ,DDL etc. ）.
• If the program is solidified outside the chip FLASH in , By ROM BootLoader Go and finish some initialization for us （ Such as phase locked loop ,DDL, peripherals ）. We can also write a secondary application , To initialize .
  
  

4.2 Set profile as default

A little

4.3 The project enters debug Pattern

• You can first test whether the communication of the simulator is normal .basic and advanced All pages have Test Connection Button .

• If the test has failed The situation of , It may be windows The drive is abnormal ,CCS The device model selected by the emulator configuration file Wait for a reason .
  

• Get into Debug Pattern .F11 Or click debug Button ,（ First meeting ） Pop up the option box , Multicore processor , We can choose only one main core first .
  

• After loading successfully ,CCS Will automatically enter main function .
  

• CPUreset, Only reset the current core ,SYSTEMreset, Reset all （ Need to use GEL File reinitialization ）.

• If this error occurs （ It's just that CCS Source file not found c）, It's not necessarily a program error . When the program exits , Into the RTS library .

• find LIB Medium RTSsrc Source code , Unpack .

• Click on Locate File, Locate the source code extracted just now .
  

• decompression RTS Source code , To the current path .
  

• remarks ： If it's debugging 6678, Be sure to bring a fan and heat dissipation . because C6678 The power consumption is very large , The fever is fast .

4.4 Hardware tracking

• Hardware Trace Analyzer
  
• PC Trace CPU The tracking . If you pass ETB（CPU Internally embedded 4KB Of buffer） The way , There is no need to control how many pins the simulator has . If it is pro Trace The way , Need simulator support （ according to buffer Space size and number of pins ）.
  
• start,trace viewer It will record the time of running each assembly command The number of clocks Cycle, wait . It is convenient to adjust the algorithm .

5. Level 1 startup mode

• The picture below is C6655 Mode of starting （C6678 One less NAND Starting mode ）
  

5.1 Data size selection

• GPIO0 Decide whether it is big end or small end . Generally, when there is network data , You can use a big way .
• Generally, it is small end byte order .
  

5.2 Starting mode 0

• GPIO321 Pin for 000, Three seeds start .
• In addition, you need to configure a phase-locked loop PLL, Reference resources 5.9

5.2.1 Subscheme -no boot

• GPIO543 = 000 .
• Subscheme 0,（ When using the simulator ）, It uses no boot. Sub mode configuration is not required .

5.2.2 Subscheme - Serial port startup

• GPIO543 = 001（uart0） and 101（uart1） .
• You need to configure the serial port baud rate , check .

5.2.3 EMIF16

• GPIO543 = 100.
• EMIF16Boot, You need to configure related .
• Chip selection , A wide , Waiting bit
  

5.3 Starting mode 1-SRIO

• GPIO321 Pin for 001,Serial Rapid I/O.
• Channel configuration ,4x1,2x2
• rate , Reference clock .
• In addition, you need to configure a phase-locked loop PLL, Reference resources 5.9
  

5.3 Starting mode 2-Eth

• GPIO321 Pin for 010, LAN startup .
• In addition, you need to configure a phase-locked loop PLL, Reference resources 5.9
  

5.4 Starting mode 3-NAND

• GPIO321 Pin for 011.

5.5 Starting mode 4-PCIe

• Failure to allocate memory may occur , Need to use IBL Start the auxiliary .
  
• Effective at startup , It can be modified in the application .
  

5.6 Starting mode 5-I2C

• In addition, you need to configure a phase-locked loop PLL, Reference resources 5.9

5.7 Starting mode 6-SPI

• In addition, you need to configure a phase-locked loop PLL, Reference resources 5.9

5.8 Starting mode 7-HyperLink

5.9 PLL configuration PLL

• 100MHz
  

6. Secondary startup mode

• IBL,Initial Boot Loader (IBL) Initial boot loader （ Secondary boot program ）
• IBL Burned on EEPROM in .
• Start by I2CEEPROM Level 1 startup , Re pass IBL Secondary boot starts the application .
• Start up time will be slower .

6.1 Why use IBL Secondary guidance

reason ：

• Solve early PLL The problem that the PLL cannot lock , Use IBL guide .（ here we are C6000 After a series of , The problem has been solved ）
• CPU Support many first level startup modes , But it is troublesome to generate images , Especially when there are many cores （ Multiple boot images are combined into one ）.
• PCIe Startup time , There may be a problem of memory allocation failure , Use IBL Assist this startup .
• Support more startup , Such as TFTP
• Multi core deployment

7. burning

• With IBL Secondary boot mode

7.1 FactoryReset Restore factory settings

• recovery EEPROM,NorFlash,NandFlash Data parameters of .
• If startup fails , You can do it first FactoryReset Return to factory , recovery IBL etc. .
  

（1） Start restoring factory settings

• Set up Flash.bat In file CCS Road strength .
• Call script Flash.bat when , You need to exit first CCS Of Debug Pattern .
• Call script , Select the development board model , Choose the simulator model
  
• Can be observed , burning EEPROM,NorFlash（ nothing , The failure ）,NANDFLASH The process of .

（2）FLASH_SPI.bat , It's directly from SPI norFlash Native startup script . from .out Format to .bin format conversion .“.OUT” The file contains a lot of debugging information , We can go through strip6x Tools （ stay C6000 Under compiler ） Remove this information .

• Need to find strip6x, Add its path to PC In the environment variables .
• perform strip6x command .
  

7.2 Use script to burn into the device

• nandFlash Burning way .
• modify Flash.bat Script , Only add parameters nand（ Can only burn nand, Not modify eeprom and nor）
  
• perform Flash.bat, Select the development board type , Simulator type . wait for ...
  
• stay GEL After file initialization , Start burning directly and automatically NAND The operation of .

7.3 Use the burning program to burn

• Modify the burning configuration file , Ensure that the burned file is consistent with the configuration file . Use notepad open nand_writer_input.txt Change file name . Modify the starting address .
• go back to CCS Environmental Science , Find the created emulator configuration file ".ccxml", Right mouse click , choice Launch Select Configuration.
  
• CCS Into Debug Pattern （PC Connect with the simulator ）
• Right click on the core 0, Connect .（ Simulator and device connection ）
• Wait for the connection to succeed .CCS Would call GEL Automatic initialization .
  
• Toolbar Load Button perhaps Run->Load->Load Program, Select burn program file “.out”, The file contains bin File parameter information .
  
• stay Memory Browser in , find Load Memory.
  
• Choose what to write bin file , Load data into memory DDR in .
  
• next step , Select the starting address ,32 A wide .
  
• Click on resume Button , Start burning .
  
• Wait for the burning to finish . Exit startup mode , Exit burn , sign out Debug Pattern .