Verilog daily question (VL2 asynchronous reset Series T trigger - Niuke network)

subject ： Realize two series asynchronous reset T trigger , The specific structure and waveform diagram are as follows ：

This question is relatively simple , Just know T The characteristics of triggers are easier to solve . namely ： Input is 1 Time value flip （0 become 1\1 become 0）, Input is 0 Time does not change .

Two in series are set as two always Block is OK , The code is as follows

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg data1;
    always @(posedge clk,negedge rst)begin
        if(!rst)  data1<=0; 
        else if(data) data1<=~data1;
        else data1<=data1;
    end

    always @(posedge clk,negedge rst)begin
        if(!rst)   q<=0;  
        else if(data1) q<=~q;
        else q<=q;
    end

//*************code***********//
endmodule

Review by the way T Trigger details Structure and characteristics ：

logic function ： Control signals T=1 when , Flip ;T=0 when , keep . The characteristic table and characteristic equation are as follows ：

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Characteristic table

  Characteristic equation ：

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Its logical symbol graphics are as follows ：

  in fact ,JK The two inputs of the trigger are connected together as T End can form T trigger .