Generic classes and parameterized classes of SystemVerilog

One Parameterized classes Parameterized classes

occasionally , It is useful to define such a class ： By passing different parameter sizes 、 Or parameter type , Can easily establish various object. There is no need to target different data sizes or types , Write duplicate similar code .

Example ：

class vector #(int size = 1);
     bit [size-1:0] a;
endclass 

vector #(10) vten; // object with vector of size 10
vector #(.size(2)) vtwo; // object with vector of size 2
typedef vector#(4) Vfour; // Class with vector of size 4

The above example , It takes the data size or size as the parameter of the class . The following example , Take the data type as a parameter .

class stack #(type T = int);
    local T items[];
    task push( T a ); ... endtask 
    task pop( ref T a ); ... endtask 
endclass 


stack is; // default: a stack of ints
stack#(bit[1:10]) bs; // a stack of 10-bit vectors
stack#(real) rs; // a stack of real numbers

SystemVerilog Templates that support writing generic code using parameterized classes . A parameter is a constant type that represents a value or data type . Once the simulation starts , You cannot change parameters . Before the simulation starts , The compiler evaluates parameter expressions as part of its refinement and code generation phases . therefore , You can use parameters as part of another type declaration , Or use the value of the parameter within the scope of the array declaration .

SystemVerilog In class header , send