[Verilog advanced challenge of Niuke network question brushing series] ~ multi bit MUX synchronizer

0. Preface

I haven't updated Niu Ke's blog for a few days , I'm busy recently , I can only try to do one watch every day ！！！ Brush the questions at the same time , Make it small on one side demo, Keep on learning .
Today's problem is mainly a multi bit data transmission across the clock domain , It is also a common question type , It works , How to deal with cross clock domain , You can move to a blog I wrote before , Portal

1. VL48 many bit MUX synchronizer

1.1 Title Description

stay data_en For the high period ,data_in Will remain unchanged ,data_en Keep at least 3 individual B Clock cycle . indicate , When data_en For the high time , Data can be synchronized .

In this question data_in The frequency of data change at the end is very low , The change between two adjacent data , At least at intervals 10 individual B Clock cycle .

1.1.1 Signal schematic diagram

1.1.2 Waveform diagram

nothing

1.1.3 Input description

input                 clk_a    , 
input                 clk_b    ,   
input                 arstn    ,
input                brstn   ,
input        [3:0]    data_in    ,
input               data_en 

1.1.4 Output description

output reg [3:0] dataout

1.2 Their thinking

According to the meaning of the topic, the general framework is as follows ：

among , The red box indicates data temporary storage as well as Enable temporary storage ; The blue box indicates cross clock domain processing , Use the shape of two beats to complete ; The green box indicates MUX Select and temporarily output the results .

1.3 Code implementation

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
    
    // The staging data_en
    reg data_en_reg;
    always @ (posedge clk_a or negedge arstn) begin
        if(!arstn) begin
            data_en_reg <= 1'b0;
        end
        else begin
            data_en_reg <= data_en;
        end
    end
    
    //data_in
    reg [3:0] data_in_reg;
    always @ (posedge clk_a or negedge arstn) begin
        if(!arstn) begin
            data_in_reg <= 4'd0;
        end
        else begin
            data_in_reg <= data_in;
        end
    end
    
    // Two beats , Transition across clock domains 
    reg data_en_ab1, data_en_ab2;
    always @ (posedge clk_b or negedge brstn) begin
        if(!brstn) begin
            data_en_ab1 <= 1'b0;
            data_en_ab2 <= 1'b0;
        end
        else begin
            data_en_ab1 <= data_en_reg;
            data_en_ab2 <= data_en_ab1;
        end
    end
    // MUX
    always @ (posedge clk_b or negedge brstn) begin
        if(!brstn) begin
            dataout <= 4'd0;
        end
        else begin
            dataout <= data_en_ab2 ? data_in_reg : dataout;
        end
    end
endmodule

1.4 The test file

To be updated ...

1.5 Simulation waveform

To be updated ...

Statement

All my series of articles , Just for learning , Not for commercial use , If there is any infringement , Please inform , To delete ！！！

I mainly record the learning process , For myself to review , Then it is to provide reference for future generations , No joy, no spray. ！！！

If it's useful to you , Remember to collect + Comment on ！！！