[high speed bus] Introduction to jesd204b

One 、 brief introduction

JESD204 It is a kind of connection data converter （ADC and DAC） High speed serial interface with logic devices , Support as much as 12.5 Gbps Serial data rate , And ensure JESD204 Links have repeatable deterministic delays . With the high speed ADC enter GSPS Range , And FPGA（ customized ASIC） The preferred interface protocol for data transmission is JESD204B.

JESD204B A standard is a layered specification . Each layer in the specification has its own function to complete .

① application layer

Support JESD204B Link configuration and data mapping .

② Transport layer

Realize the mapping between the converted samples and the framed undisturbed octets . It takes the original sample data and packages it in some way , With jesd204b Standards for , And distribute this data to different channels .

③ Data link layer

The optional scrambled octet word is encoded into 10 Bit character . This layer is also where control characters are generated or detected , The purpose is to monitor and maintain channel alignment .

④ The physical layer

Serializer / String unloader (SERDES) layer , Responsible for sending or receiving characters at line rate . This layer includes a serializer 、 Driver 、 Receiver 、 Clock and data recovery circuit .

notes ： The scrambling layer can selectively acquire octets and scramble or descramble them , So as to reduce by extending the spectrum peak EMI effect . Scrambling is done in the transmitter , Descrambling is done in the receiver .

Each link supports at most 32 Channels , Each channel can transmit up to 12.5Gb/s Raw data , It not only describes how to A To B Get bit , It also describes the bit representation meaning of how to map samples to these high-speed channels , Data can be synchronously transmitted .

 

Subclass 0：

Deterministic delay is not supported

Subclass 1：

Support deterministic delay , Take advantage of the external SYSREF As a clock signal .

The basic idea is SYSREF After the rising edge of , The next rising edge of the device clock is called the time reference point , The internal frequency divider may be reset to the starting value , Sometimes it takes more than one SYSREF Signal to reset

 

Subclass 2：

Support deterministic delay , utilize ~SYNC As a clock signal ;

~SYNC The role of ： Request initialization sequence , For its data 、 Serializer and deserializer , This method is not applicable to higher frequencies .