RISC CPU design based on FPGA (4) 36 questions about the project and their answers

        CPU Micro architecture ？ALU Out of the data path ,IDec Out of the control path , Various functional components , They are connected with each other through data path and control path CPU Micro architecture ;

         Number of instructions ？33 individual （RISC Reduced instruction set architecture ）;

         Command width ？12 position （= Instruction word length ）;

         Data width ？8 position （= Machine word length = The width of the register ）;

         Harvard architecture ？ Instruction bus and data bus are independent , The width of instructions and data can be different , This improves bandwidth

         What is a bus ？ Bus is a group of information transmission paths that can be shared by multiple components in time-sharing ;

         Instruction memory ？2K X 12（EPROM）（= Program memory ）;

         Data storage ？72 X 8（RAM）（= General registers = Register file = Register heap ）;

        Addressing mode ？ Memory is byte addressed ;

         The small end model ？ The small address corresponds to the low order of the data ;

         special function register ？8 individual &