input_ delay

0 Preface

Fundamentals of time series analysis , The underlying principle ：
The timing should meet latch Of setup&hold Time . The data cannot change within the required stable window .
Basic timing model
Stack(setup)= T-Tsu-Tco-Tdata adjacent 2 A clock
Stack(hold )= Tco + Tdata - Thd Same as 1 A clock
If Tco and Tdata The delay gets bigger , Retention time Stack (hold) More margin
When there is a hold Violation , Can increase Tdata Routing length to eliminate .
If Tco and Tdata The delay gets bigger , Set up time Stack (setup) The less margin

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1 input delay analysis

FPGA Pin From the perspective of

input delay Describe the data port stay latch Look at the edge of the clock , How long did it take for the data to stabilize .
max_delay( analysis setup)
min_delay( analysis hold )

1.1 input delay The classification of

System synchronization is divided into 3 Kind of ：(SDR Rising edge 、SDR Falling edge 、DDR)x( Edge alignment )
Source synchronization is divided into 6 Kind of ：(SDR Rising edge 、SDR Falling edge 、DDR)x( Center alignment 、 Edge alignment )
External devices may provide Tco\setup\hold\shew
Hidden points needing attention ：

1. The source synchronization edge alignment is on the receiving side by default (FPGA) In memory PLL Phase shift 180 degree .
2. System synchronization only has edge alignment , No center alignment .

1.2 Tdly The definition of

It's going on intput delay The delay of clock path and data path should be considered when calculating ,
and FPGA Look at , You only need to know the delay of the data relative to the clock , Then the clock delay can be regarded as 0,
And the clock path delay is compensated to the data path delay to get Tdly,Tdly= Data path - Clock path . This can reduce the variables of analysis .

1.3 summary

1. Rising edge does not add -clock_fall , The default is the rising edge . The difference between the falling edge and the rising edge is to add -clock_fall .
2. DDR There are more constraints -clock_fall -add_delay
3. It describes the coordinate time , The second part is the absolute difference . With latch by 0 moment .

2 The specific content

2.1 System synchronization

The data synchronized by the system appears in launch Along the back ,latch Is the next edge

2.1.1 SDR Rising edge

 It is known that ：
 Clock name    : clk_in
 data port : din
T   =10ns
Tco =1~2ns
Tdly=0.3~0.4ns
 obtain ：
set_input_delay  -clock clk_in  -max  2.4  [get_ports  din]
set_input_delay  -clock clk_in  -min  1.3  [get_ports  din]
 It's important to note that  -max 2.4  instead of   -max_delay 2.4

2.1.2 SDR Falling edge

 It is known that ：
 Clock name    : clk_in
 data port : din
T   =10ns
Tco =1.5~2ns
Tdly=0.3~0.4ns
 obtain ：
set_input_delay  -clock clk_in  -max 2.4  [get_ports  din] -clock_fall 
set_input_delay  -clock clk_in  -min 1.8  [get_ports  din] -clock_fall 

2.1.2 DDR

It is known that ：
Clock name : clk_in
data port : din
T =10ns
Tco =1.0~2ns Rising edge
Tco =1.5~2ns Falling edge
Tdly=0.3~0.4ns
obtain ：
set_input_delay -clock clk_in -max 2.4 [get_ports din]
set_input_delay -clock clk_in -min 1.3 [get_ports din]
set_input_delay -clock clk_in -max 2.4 [get_ports din] -clock_fall -add_delay
set_input_delay -clock clk_in -min 1.8 [get_ports din] -clock_fall -add_delay
// There is a point of knowledge ： The data initiated by the falling edge is sampled on the next rising edge . therefore data path It's from 5 Start .

2.2 Source synchronization

2.2.1 Source synchronization Center alignment

Center aligned latch Edge is the next rising edge of the rising edge in the figure . You can see input_delay The range is [dv_are,T-dv_bre], Because the clock is periodic .

2.2.1.1 Rising edge

set_input_delay -clock [get_clocks clk_in] -min -add_delay 1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 9.0 [get_ports din]

2.2.1.2 Falling edge

set_input_delay -clock [get_clocks clk_in] -clock_fall -min -add_delay 1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -clock_fall -max -add_delay 9.0 [get_ports din]

2.2.1.3 DDR

set_input_delay -clock [get_clocks clk_in] -clock_fall -min -add_delay 1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -clock_fall -max -add_delay 4.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -min -add_delay 1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 4.0 [get_ports din]

2.3.2 Source synchronization edge MMCM alignment

MMCM It has the function of adjusting clock phase .latch Edge is the rising edge in the figure ,ltach The data of is the data after the rising edge .

2.3.2.1 Rising edge

set_input_delay -clock [get_clocks clk_in] -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 1.0 [get_ports din]

2.3.2.2 Falling edge

-clock_fall

2.3.2.3 DDR

set_input_delay -clock [get_clocks clk_in] -clock_fall -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -clock_fall -max -add_delay 1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 1.0 [get_ports din]

2.3.3 Source synchronization Align the edges directly

2.3.3.1 Rising edge

set_input_delay -clock [get_clocks clk_in] -min -add_delay 9.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 11.0 [get_ports din]

2.3.3.2 Falling edge

-fall_clock

2.3.3.3 DDR

set_input_delay -clock [get_clocks clk_in] -clock_fall -min -add_delay 4.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -clock_fall -max -add_delay 6.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -min -add_delay 4.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 6.0 [get_ports din]

experiment

Unconstrained input_delay Compiled results of

 No constraints added ,slack = infinite , That is, unable to analyze .

add to DDR input delay constraint

vivado Analyze the worst path ( Rising edge and falling edge hold Can be satisfied ) That is, the falling edge sends data , Rising edge sampling .
data path The starting point of the launch Along is 5.0ns It indicates that the data analyzed is the data initiated by the falling edge . entered 3.091ns arrive reg.D
from destination clock path The window sees ,latch Along is 10.0ns, Just in line with the falling edge to send data , Rising edge sampling .
Clock from clk_in port after bufg Wait for the delay , subtracting setup You can get required time. You can see setup It's very small. It's just 0.007ns.

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contrast
use MMCM edge Source synchronization
set_input_delay -clock [get_clocks clk_in] -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 1.0 [get_ports din]
direct edge Source synchronization
set_input_delay -clock [get_clocks clk_in] -min -add_delay 9.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 11.0 [get_ports din]
What's the difference between the two ？ It feels like there is a cycle difference .
Use the following constraints , Don't add MMCM Will report a mistake hold See the screenshot below , See that the clock path is too long
set_input_delay -clock [get_clocks clk_in] -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 1.0 [get_ports din]


When using the following constraints , Yes setup Report errors
set_input_delay -clock [get_clocks clk_in] -min -add_delay 9.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay 11.0 [get_ports din]

contrast

##  constraint 1：
set_input_delay -clock [get_clocks clk_in] -min -add_delay -1.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay  1.0 [get_ports din]
##  constraint 2：
set_input_delay -clock [get_clocks clk_in] -min -add_delay  9.0 [get_ports din]
set_input_delay -clock [get_clocks clk_in] -max -add_delay  11.0 [get_ports din]

constraint 1 And constraints 2 Compare , What's the difference between the two ？ It feels like there is a cycle difference 10ns.

Conclusion ：
Use constraints 1,vivado Default latch The clock along is 0ns Of , The clock path is from 0ns Start accumulation . At present launch Is the current latch,
Use constraints 2,vivado Default latch The clock along is 10ns Of , The clock path is from 10ns Start accumulation .
Of the two latch The clock differs by one cycle T=10ns.

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Reference resources

https://my.oschina.net/msxbo/blog/3122304