Makefile knowledge rearrangement (super detailed)

Preface

This is for me xmind turn markdown The effect of , I feel very bad , Attach mind map
Mind mapping was also my last visit CSDN 了 ：makefile Knowledge rearrangement （ Hyperdetail ）

makefile

Compilation Rules

Target file

Dependency file

Command line

characteristic

1. Only the relevant commands of the updated program file will be executed , If you haven't updated ,make Instructions will not be executed （ Increase of efficiency ）

2. Variable name instead of file name , Usually multiple file names , Use $ Replace

obj = a.o b.o
test : $(obj)
cc -o test $(obj)
a.o:a.c b.h
cc -c a.c
b.o:b.c
cc -c b.c

3.makefile Try to capitalize commands , namely Makefile

#Makefile1
main:main.c add.c sub.c
gcc $^ -o [email protected]

4.makefile of use # notes

#Makefile1
main:main.c add.c sub.c
gcc $^ -o [email protected]

#Makefile2
main:main.o add.o sub.o
gcc $^ -o [email protected]
main.o:main.c
gcc -c main.c
add.o:add.c
gcc -c add.c
sub.o:sub.c
gcc -c sub.c
.PHONY:clean
clean:
rm -f main.o add.o sub.o main

5. Add... Before the order @, At run time , You can hide the executed commands

hello:hello.o
@gcc hello.o -o hello
hello.o:hello.c
@gcc -c hello

6.echo The command is equivalent to printing

hello:hello.o
@gcc hello.o -o hello
@echo make done!
hello.o:hello.c
@gcc -c hello
@echo make done!

Variable definitions

Simple Assignment ( := ) In programming language, the normal way of understanding assignment , Valid only for variables in the current statement .

Recursive assignment ( = ) Assignment statements can affect multiple variables , All other variables related to the target variable are affected .（ amount to C++ Citation in ）

Conditional assignment ( ?= ) If the variable is undefined , The value in the symbol is used to define the variable . If the variable has been assigned , The assignment statement is invalid .（ Only undefined variables can be defined ）

a1 := a.o
a1 ?= b.o

Invalid definition , Because it has been defined before

Additional assignment ( += ) The original variable is added with a new value separated by spaces .（ and C Language += similar ）

a1 = a.o;
a1 += b.o;

a1 = a.o b.o

Special characters

Illustrate with examples

TARGET?=demo
OBJS:=main.o add.o sub.o
CC:=gcc
CFLAGS:= -c -o
CFLAGSs:=-o
$(TARGET):$(OBJS)
$(CC) $(OBJS) $(CFLAGSs) $(TARGET)
%.o:%.c
$(CC) $< $(CFLAGS) [email protected]
clean:
rm $(OBJS) $(TARGET)

• $(CC) $< $(CFLAGS) [email protected]

Use the first three more

• [email protected] Indicates the name of the target file , Include extension
• $^ Represents all dependent files , Space off , No repetition
• $< Indicates the name of the first dependent file
• $+ Represents all dependent files , Whitespace separated , Can be repeated
• $* Indicates the name of the target file , Does not contain extension
• $? Dependency , All dependent files newer than the target file

Pseudo instruction

Meaning of being

• stay Makefile in ,.PHONY hinder target It's also a fake target, Rather than a real file target, Be careful Makefile Of target The default is file .
• If you have the same file name , Such as clean, Will continue to execute pseudo instructions

Practical application

• .clean

  .PHONY:clean
  clean:
  rm -rf *.o test

  • Clear files ：make clean

• .install

  .PHONY: install
  install:
  mkdir $(test_dir)
  cp test $(test_dir)

  • Line command ”make install“ after ,Make Will execute commands in sequence ”mkdir $(test_dir)“ and ”cp test $(test_dir)“, hold test File copy to test_dir Variable to the specified directory

• .uninstall

  .PHONY: uninstall
  uninstall:
  rm -rf $(test_dir)

  • Delete the specified directory and all the files in it

• .all

  .PHONY: all
  all: test $(obj)

  • Make Will be able to all As the ultimate goal . Because the pseudo target and the real target have dependent files

wildcard

Makefile Wildcard in ：* and %

• • Represents all first-class files

    test:*.c
    gcc -o [email protected] $^
    # be-all .c file

• %（ Examples of special characters ）

  • test:test.o test1.o
    gcc -o [email protected] $^
    %.o:%.c
    gcc -o [email protected] $^

    “%.o” Put all we need “.o” The files are combined into a list , Each file taken one by one from the list ,“%” Indicates the file name of the extracted file （ No suffix ）, Then find the file and "%" With the same name “.c” file , Then execute the following command , Until all the files in the list are taken out .

conditional

ifeq

• Judge whether the parameters are not equal , Equal to true, Unequal false.

ifneq

• Judge whether the parameters are not equal , Unequal true, Equal to false.

ifdef

• Judge whether there is value , It's worth it true, No value is false.

ifndef

• Judge whether there is value , No value is true, It's worth it false.

File search

VPATH and vpath

• difference

  • VPATH You need to specify the path of the file when you use it ;vpath Is the key word , When searching, you not only need to add the path of the file , It is also necessary to add corresponding restrictive conditions .

    VPATH It's a variable. , More specifically, environment variables ,Makefile A special variable in , When using, you need to specify the path of the file ;vpath Is the key word , Search by pattern , It can also be said to be selective search . When searching, you not only need to add the path of the file , It is also necessary to add corresponding restrictive conditions .

• VPATH

  VPATH = /home/b
  obj = a.o b.o
  .PHONY : all
  all:test $(obj)test:$(obj)
  cc -o test $(obj)

  • Format ：VPATH := /src:/car

    First search /src, Re search /car
    It can be understood in this way , hold src Is assigned to a variable VPATH

  • Be careful ： No matter how many paths are defined ,makefile Will first look under the current directory , eureka , Will not arrive VPATH Keep looking for

• vpath

  • Format ：vpath Pattern Catalog ： Catalog …
  • vpath test.c /src :/car

• other

  • vpath test.c

    • It means to clear the compliance file test.c Search directory for

  • vpath

    • vpath Making it alone means clearing all the file search paths that have been set

Common functions

wildcard

• SRC = $(wildcard .c ./foo/.c)

  Search the current directory and ./foo/ All to .c Final document , Generate a list of file names separated by spaces , And assign it to SRC. The current directory file only has a file name , The file name under the subdirectory contains path information , such as ./foor/bar.c.

patsubst

Makefile Content

all:
@echo $(patsubst %.c,%.o,programA.c programB.c)

bash In the implementation of make

$ make
programA.o programB.o

• $(patsubst ,, )

  function : lookup The words in ( Words with " Space ", “tab”, " Line break " To segment ) Compliance , In line with the word , use replace .

notdir

Makefile Content

all:
@echo $(notdir /home/a.c ./bb.c …/c.c d.c)

bash In the implementation of make

$ make
a.c bb.c c.c d.c

• $(notdir <names…>)

function : From the file name sequence Take out the non directory part of
return : File name sequence The non directory part of

XMind: ZEN - Trial Version