[quick start of Digital IC Verification] 9. Finite state machine (FSM) necessary for Verilog RTL design

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One 、 The basic theory

State machine Shorthand for FSM（ Finite State Machine）, Also known as synchronous finite state machine , We usually call it state machine for short , Reason why “ Sync ” Because all state jumps in the state machine are carried out under the action of the clock , and “ Co., LTD. ” It means that the number of States is limited . State machines are divided into two categories according to the reasons that affect the output , namely Moore State machine and Mealy State machine , What they have in common is ： The jump of state is only related to input . The difference is mainly in the output ： If the final output is only related to the current state and has nothing to do with the input, it is called Moore State machine ; If the final output is related not only to the current state but also to the input, it is called Mealy State machine . State machine is a very important application in sequential logic circuit , It is often used in large and complex systems .

Two 、 Automatic beverage vending machine

2.1、 Problem description

Design an automatic beverage machine , Set the price of drinks 2.5 element , You can use 5 Angular sum 1 Yuan coins , With change function .

notes ： You can only cast at the same time 1 Yuan or 5 horn , You can't throw two at the same time .

2.2、 Functional block diagram and interface definition

Interface signal definition

• clk： Clock input
• reset： System reset signal
• half： input 5 Dimes
• one： input 1 Yuan coins
• cout： Change signal
• out： The machine sells drinks

2.3、 State transition diagram - moore FSM

notes ：Moore FSM characteristic ： The output is only related to the current state , It has nothing to do with input ！

Moore FSM Of RTL Code

module drink_status_moore(
    input   wire    clk,
    input   wire    reset,
    input   wire    half,
    input   wire    one,
    
    output  wire    out,
    output  wire    cout
);


parameter [2:0] S0 = 3'b000,
                S1 = 3'b001,            
                S2 = 3'b010,     
                S3 = 3'b011,     
                S4 = 3'b100,     
                S5 = 3'b101,     
                S6 = 3'b110;    

reg [2:0]   curr_state;
reg [2:0]   next_state;


//first segment:state transfer
[email protected](posedge clk or negedge reset)
    if(!reset)
        curr_state <= S0;
    else
        curr_state <= next_state;

//second segment:transfer condition
[email protected](*)
	case(curr_state)
		S0	:	if(half == 1'b1)		next_state = S1;
				else if(one == 1'b1)	next_state = S2;
				else					next_state = S0;
		
		S1	:	if(half == 1'b1)		next_state = S2;
				else if(one == 1'b1)	next_state = S3;
				else					next_state = S1;
		
		S2	:	if(half == 1'b1)		next_state = S3;
				else if(one == 1'b1)	next_state = S4;
				else					next_state = S2;
		
		S3	:	if(half == 1'b1)		next_state = S4;
				else if(one == 1'b1)	next_state = S5;
				else					next_state = S3;
		
		S4	:	if(half == 1'b1)		next_state = S5;
				else if(one == 1'b1)	next_state = S6;
				else					next_state = S4;
		
		S5	:							next_state = S0;
		
		S6	:							next_state = S0;
		
		default :						next_state = S0;
	endcase

//third segment:state output
//moore type FSM
assign out = ((curr_state == S5) || (curr_state == S6) ) ? 1'b1 : 1'b0;

assign cout = (curr_state == S6) ? 1'b1 : 1'b0;
	
endmodule

FSM Three paragraph writing ：

• Good coding style
• Logic synthesis
• Readable stars

2.4、 State transition diagram - Mealy FSM

notes ：Mealy FSM characteristic ： The output is not only related to the current state , It is also related to input ！

• Mealy It only took 5 States , But the output control will become complex ！

Mealy FSM Of RTL Code

module drink_status_mealy(
    input   wire    clk,
    input   wire    reset,
    input   wire    half,
    input   wire    one,
    
    output  wire    out,
    output  wire    cout
);


parameter [2:0] S0 = 3'b000,
                S1 = 3'b001,            
                S2 = 3'b010,     
                S3 = 3'b011,     
                S4 = 3'b100,     
                S5 = 3'b101,     
                S6 = 3'b110;    

reg [2:0]   curr_state;
reg [2:0]   next_state;


//first segment:state transfer
[email protected](posedge clk or negedge reset)
    if(!reset)
        curr_state <= S0;
    else
        curr_state <= next_state;

//second segment:transfer condition
[email protected](*)
	case(curr_state)
		S0	:	if(half == 1'b1)		next_state = S1;
				else if(one == 1'b1)	next_state = S2;
				else					next_state = S0;
		
		S1	:	if(half == 1'b1)		next_state = S2;
				else if(one == 1'b1)	next_state = S3;
				else					next_state = S1;
		
		S2	:	if(half == 1'b1)		next_state = S3;
				else if(one == 1'b1)	next_state = S4;
				else					next_state = S2;
		
		S3	:	if(half == 1'b1)		next_state = S4;
				else if(one == 1'b1)	next_state = S0;
				else					next_state = S3;
		
		S4	:	if(half == 1'b1)		next_state = S0;
				else if(one == 1'b1)	next_state = S0;
				else					next_state = S4;
		
		default :						next_state = S0;
	endcase

//third segment:state output
//mealy type FSM
assign out = ((curr_state == S3 && one == 1'b1) || (curr_state == S4 && (half==1'b1 || one==1'b1)) ) ? 1'b1 : 1'b0;

assign cout = (curr_state == S4 && one == 1'b1) ? 1'b1 : 1'b0;
	
endmodule

2.5、 Finite state machine circuit logic diagram

2.6、 Finite state machine summary

• FSM Design steps of finite state machine
  • Interface definition
  • State definition and coding
  • Transition diagram of state
  • According to the three segment coding style RTL Code
• To write TestBench Code
• Use Questasim Compile and simulate
• Check the input excitation through the waveform tool 、 Status signal and output signal

Frequently asked questions ： Finite state machine classification ？

• answer ：Moore State machine ： The output of the state machine is only related to the current state
• Mealy State machine ： The output of the state machine is not only related to the current state , Also related to the current input

Frequently asked questions ： The difference between the two state machines ？

• answer ：1、Moore State machine ： After a finite gate delay of the clock pulse , The output is stable . The output will remain stable for a complete clock cycle , Even if the input signal changes within this clock , The output signal will not change . transport The influence of input on output can only be reflected in the next clock cycle . Separate input and output , yes Moore Important features of state machines .
• 2、Melay State machine ： Because the output is directly affected by the input , The input can change at any time of the clock cycle , This makes the output state ratio Moore The output state of the state arrives one cycle in advance . The noise of the input signal may appear on the output signal .
• 3、 For the same circuit , Use Moore State machine design may be better than using Mealy The state machine has more States .

The key to state machine writing , Write in three parts ：

• 1、 The first part is responsible for ： State jump
• 2、 The second part is responsible for ： Jump conditions
• 3、 The third part is responsible for ： The output signal

2.7、 Something to be aware of ：full case

• Define the complete state , Even some states may not appear in the circuit
• The purpose is to avoid the occurrence of Combinational logic ring
  • Combinational logic rings can lead to STA There's no way to analyze ,DFT There is no way to cover
  • Asynchronous timing （timing The path cannot be constrained , There is no way to analyze ） The problem of

3、 ... and 、 Actual test ： Sequence detector

3.1、 Functional requirements of sequence detector

• The design requirements
  • Design sequence detector with state machine （1110010）
• Design function
  • Design a sequence detector , The sequence of detection is “1110010”
  • When the input signal X In turn “1110010” when , The output signal Y Output a high level
  • Otherwise, the output signal Y Low level

notes ： Sequence detectors are often used in Engineering , be used for Detect sequence header ！

3.2、 Timing diagram of timing detector

3.3、 State transition diagram of timing detector

Look for the , The output is independent of the input , This is a Moore State machine ！

3.4、 Reference code of sequence detector

RTL Reference code

// 1110010
module seq(
    input   wire            in,
    input   wire            clk,
    input   wire            reset,
    
    output  wire            out
);



parameter [2:0] S0 = 3'b000,
                S1 = 3'b001,            
                S2 = 3'b010,     
                S3 = 3'b011,     
                S4 = 3'b100,     
                S5 = 3'b101, 
				S6 = 3'b110,				
                S7 = 3'b111;    
			

reg [2:0]   cur_state;
reg [2:0]   next_state;

 
//first step: state transfer
[email protected](posedge clk or negedge reset)
    if(~reset)
        cur_state <= S0;
    else
        cur_state <= next_state;


//second: transfer condition
[email protected](*)
    case(cur_state)
        S0:begin
            if(in == 1) next_state = S1;
            else        next_state = S0;
        end
        
        S1:begin
            if(in == 1) next_state = S2;
            else        next_state = S0;
        end
        
        S2:begin
            if(in == 1) next_state = S3;
            else        next_state = S0;
        end
        
        S3:begin
            if(in == 0) next_state = S4;
            else        next_state = S3;
        end
        
        S4:begin
            if(in == 0) next_state = S5;
            else        next_state = S1;
        end
        
        S5:begin
            if(in == 1) next_state = S6;
            else        next_state = S0;
        end
        
        S6:begin
            if(in == 0) next_state = S7;
            else        next_state = S2;
        end
        
        S7:begin
            if(in == 0) next_state = S0;
            else        next_state = S1;
        end
        
        default:        next_state = S0;
    
    endcase

//third: output
assign out = (cur_state == S7) ? 1'b1 : 1'b0;

endmodule

TestBench Reference code

`timescale  1ns/1ns

module  tb_led();

//reg define
reg     clk;
reg     rst_n;
reg     C;

//wire  define
wire    Y;


// // Initialize the system clock 、 Global reset 
initial begin
    clk    = 1'b1;
    rst_n <= 1'b0;
	
    #10
    rst_n <= 1'b1;
end

always  #5 clk = ~clk;

[email protected](posedge clk or negedge rst_n)
    if(rst_n == 1'b0)
        C <= 1'b0;
    else
        C <= {$random} % 2;

seq  seq_inst(
    .clk      (clk    	),  
    .reset    (rst_n  	),  
    .in 	  (C   		), 
     
    .out      (Y    	)   
);

endmodule

The selected simulation results are as follows ：

Reference resources

• 《 Wildfire journey Altera EP4CE10 - State machine 》
• Combinational logic ring （Combinational Loop）
• State machine , Start with the details （ One stage 、 Two-stage type 、 Three paragraph ,moore type 、mealy type ）