CPU design related notes

1. Simply talk about the assembly line CPU

Single launch static five stage pipeline CPU：
Fingering (IF)-> decoding (ID)-> perform (EXE)-> Visiting and depositing (MEM)-> Write back to (WB)
Assembly line CPU The essence of design is understood as a workshop for assembly line production , One stage completes a specified function alone .
（1） Time flows
Take five sections of running water as an example , The fifth paragraph is ： Fingering - decoding - Visiting and depositing - perform - Write back
Treat each paragraph as a part , When the previous instruction goes from fetch to decoding , That is, start to fetch the next instruction .

（2） Space water
Analogy time flow , It is simply understood as expanding each part to the original work efficiency n times ; That is to say, one instruction is taken at a time in the finger fetching stage , Now you can take it at once 2 One or more .

2. Assembly line CPU Instruction correlation in and pipeline conflict

3. Solve the assembly line CPU Data related conflict method in design

(1) Blocking technology

Simple understanding ： Let a level of the next instruction stop and wait for the last pending result of the above instruction , That is, wait until the above instructions have completely completed the five level pipeline operation .
And “ Read after writing ” Related conflicts ： That is, the upper level has not written registers or data RAM The next instruction that follows already needs this new value in the execution phase .

Blocking technology ： Let the next instruction wait for the last instruction to complete the whole instruction in the execution stage .

(2) Forward delivery technology

Simple understanding ： Send the results to be used directly to the corresponding flow stage through a dedicated path , Don't wait for the writeback operation of the last paragraph .
Solution and “ Read after writing ” Related conflicts ：

Forward delivery technology ： The result of the previous instruction to be written will be sent directly to the pipeline stage of the next instruction .
I send the fresh addition result just released directly to the next instruction to eat . That's what's called Internal push forward (Internal Forwarding), Or internal bypass (Bypass).

reference ：

《CPU Design practice 》 Wang Wenxiang Xing Jinzhang Writing
《 Fundamentals of computer architecture The third edition 》 Hu Chuanwu waited
《 Computer principle and design ：Verilog HDL edition 》 Written by Li Yamin