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数字IC手撕代码--投票表决器
2022-07-02 13:24:00 【FPGA硅农】
题目
设计一个投票表决器,输入为一个5bit的向量,为1表示赞同,为0表示不赞同,当赞同人数大于非赞同人数时,表决器输出为1,否则为0。
思路:一种方法是统计向量中1的个数,若大于等于3,则输出1,否则输出0。另一种方法是考虑所有可能的情况,事实上,只要有三个位的值为1,则表决器就输出1,因此可据此进行枚举( C 5 3 = 10 C_5^3=10 C53=10),得到最终的结果。
代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2022/07/01 15:19:05
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(
input logic clk,
input logic rst,
input [4:0] vote,
output logic r1,
output logic r2
);
//1
[email protected](posedge clk,posedge rst)
if(rst)
r1<=0;
else
r1<=(vote[0]&vote[1]&vote[2])
|(vote[0]&vote[1]&vote[3])
|(vote[0]&vote[1]&vote[4])
|(vote[0]&vote[2]&vote[3])
|(vote[0]&vote[2]&vote[4])
|(vote[0]&vote[3]&vote[4])
|(vote[1]&vote[2]&vote[3])
|(vote[1]&vote[2]&vote[4])
|(vote[1]&vote[3]&vote[4])
|(vote[2]&vote[3]&vote[4]);
//2
logic s1;
logic c1;
logic s2;
logic c2;
logic [2:0] sum;
assign {
c1,s1}=vote[0]+vote[1]+vote[2];
assign {
c2,s2}=vote[3]+vote[4];
assign sum={
c1,s1}+{
c2,s2};
[email protected](posedge clk,posedge rst)
if(rst)
r2<=0;
else if(sum>=3)
r2<=1;
else
r2<=0;
endmodule
测试平台
module test;
logic clk;
logic rst;
logic [4:0] vote;
logic r1;
logic r2;
logic error;
//clk
initial
begin
clk=0;
forever
#5 clk=~clk;
end
//rst
initial
begin
rst=1;
#100
rst=0;
end
//
[email protected](posedge clk,posedge rst)
if(rst)
vote<=0;
else
vote<=$urandom%32;
//
assign error=(r1!=r2)?1:0;
top U(.*
/* input logic clk, input logic rst, input [4:0] vote, output logic r1, output logic r2 */
);
endmodule
结果

总结
对于N输入的表决器(N为奇数),我们同样可以采用类似的方法:
1.通过加法器求1的个数,若和大于(N-1)/2,则输出为1
2.枚举这N个输入的(N+1)/2组合(共 C N ( N + 1 ) / 2 C_N^{(N+1)/2} CN(N+1)/2项),然后将它们或起来。
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