System Verilog implements priority arbiter

subject

share 8 A request , Each request corresponds to a priority , Now design an arbiter , Output according to priority grant vector （ The higher the value, the higher the priority ）.
Ideas ： We design a module , The module has 2 Data input ports （ Input data added req Of “{req,weight}”）, And two index input ports , These two indexes correspond to two data , The output of the module is the larger value of the two data and the index corresponding to the larger value .

Code

Basic modules ：

module comp
#(DATA_WIDTH=32)
(
input logic clk,
input logic [DATA_WIDTH:0] data_a,
input logic