Makefile demo

make Tools are a basis makefile The contents of the document , Target （ Executable file ） Perform dependency detection （ What intermediate files are required before generating the executable ） And perform the relevant actions （ Compile etc. ） Tools for . And this makefile The file is similar to a script , The content includes make Processing actions to be performed and dependencies .

makefile The main content to be carried out is to clarify the goal 、 Clarify what the goal depends on 、 Specify that the corresponding processing actions should be performed when the dependency conditions are met . For example, we will finally realize a This goal , But you have to rely on b, and b Depend on c The existence of , Can be described as ：

a:b

cmdbtoa

b:c

cmdctob

“：” On behalf of dependence , In addition, you should use before each processing action tab The key to separate . The four lines above mean ：a Depend on b, And deal with cmdbtoa;b Depend on c, And deal with cmdctob.

gcc Yes C/C++ Compilation process , It is divided into four parts , Preprocessing , compile , assembly , link .

makefile1:

C = gcc
G = g++
CFLAGS = -Wall -O -g
TARGET = ./test

# Means to put all .c、.cpp File compiled into .o file .	 
# $ @ Expand to the destination file name of the current rule 
# $ < Expand to the first dependency file in the dependency list 
# $^ Expand to the entire list of dependencies （ Get rid of all duplicate file names ）.
%.o:%.c
	$(C) $(CFLAGS) -c $< -o [email protected]

%.o:%.cpp
	$(G) $(CFLAGS) -c $< -o [email protected]

# Means to generate an all with .c、.cpp List of files at the end , Then store the variable SOURCES in . 
SOURCES = $(wildcard *.c *.cpp)
# hold SOURCES All files in the file list .cpp become .o、.c become .o, Then form a new list , Deposit in OBJS Variable . 
OBJS = $(patsubst %.c,%.o,$(patsubst %.cpp,%.o,$(SOURCES)))

$(TARGET):$(OBJS)
	$(G) $(OBJS) -o $(TARGET)
	#chmod a+x $(TARGET)  Express the firstTest Force into executable 
	chmod a+x $(TARGET)

clean:
	rm -rf *.o test

makefile2:

#“：” On behalf of dependence , In addition, you should use before each processing action tab The key to separate .
OBJS = test1.o test2.o
G = gcc
# CFLAGS = -Wall -O -g  Configure compiler settings , And assign it to CFLAGS Variable 

# -Wall： Output all warning messages 

# -O： Optimize at compile time 

# -g： Represents compilation debug edition 
CFLAGS = -Wall -O -g

test:$(OBJS)
	$(G) $(OBJS) -o test

test1.o:test1.c test2.h
	$(G) $(CFLAGS) -c test1.c
test2.o:test2.c test2.h
	$(G) $(CFLAGS) -c test2.c

clean:
	rm -rf *.o test