VHDL implementation of single cycle CPU design

VHDL Realize single cycle CPU Design
stay quartus achieve , The top level is schematic mode , Language use VHDL, Realize single cycle CPU The function of , Include ALU,RAM,ROM,MUX,regfile Equal module , Below are engineering screenshots and simulation screenshots .

Simulation screenshot ：

ALU Module code ：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_lrt is
port(a,b:in std_logic_vector(15 downto 0);
func:in std_logic_vector(3 downto 0);
c_lrt:out std_logic_vector(15 downto 0));
end ALU_lrt;
architecture behave of ALU_lrt is
begin
process (a,b,func)
begin
case func is
when “0000”=>c_lrt<=a and b;–and
when “0001”=>c_lrt<=a or b;–or
when “0010”=>c_lrt<=a xor b;–xor