Cadence learning records

Based on the experimental class cadence A little record of zero foundation introductory learning

One . IC Design process ：

classification ： Full customization (full custom)、 Semi custom (semi-custom) And based on programmable devices ( programmable device) Of IC Design . Analog integrated circuits are generally realized by full customization .

1. Full customization ：① The purpose is to maximize and optimize circuit performance , But it takes a long time , Suitable for mass production , High integration is required 、 Fast 、 Small area 、 General purpose with low power consumption IC or ASIC.② Designers are required to complete the circuit construction based on transistor level , All devices and interconnection layouts are designed by hand .
2. Semi custom ： Based on gate array ( gate array) And standard units ( standard-cell) The process of , Its cost is low 、 Cycle is short 、 Low chip utilization , Suitable for small batch 、 Fast chip .
3. be based on PLD or FPGA And other programmable devices IC Design pattern is a kind of “ Rapid prototyping design ”, Programmable logic devices are usually semi-finished chips provided by semiconductor manufacturers , The manufacture of logic gate array has been completed , And the connection circuit between logic gates can pass EDA Tools / Programming to control on and off .

technological process ： Determine the circuit design index —— Drawing circuit diagrams schematic—— Circuit simulation （ Pre simulation ）—— Generate layout —— Design rule check (DRC)—— Comparison between layout and circuit schematic (LVS) Check —— Parasitic parameter extraction ( LPE)—— Post simulation —— Tape-out 、 Packaging and testing

EDA Tools ： Mostly in the United States Cadence、Synopsis（HSpice) and Mentor Graphics The products of the three companies are mainly

Two . Cadence Use

Design platform ADE、 Circuit schematic editor (virtuoso schematic editor)、 Circuit simulator (spectre)、 Layout editor (virtuosolayouteditor)、 Layout verification tool (dracula) etc. . meanwhile ,ADE The design platform provides interfaces for other products , Such as Hspice Emulator 、Calibre Tools and their own layout checking tools Assura etc. , Can be integrated into the design platform .

• start-up cadence： Turn on the virtual machine , Right click , left-click “open terminal”—— Input “icfb“ or “virtuoso”（ Notice that it's lowercase ）, enter

remarks

• Pre simulation ： No parasitic parameters are added to the net list , Pre layout simulation ( pre-layout simulation)
• The post simulation library obtains a delay 、 Power waste 、 logic function 、 Time sequence and other information
• Before simulation, we need to build the circuit structure and test platform and define each device 、 Excitation source parameters and required simulation type , Then call the circuit simulator , Such as HSPICE、SPECTRE、TSPICE The net list is automatically generated by the software for simulation .
• Parasitic parameter extraction ： Consider parasitism R、C、L
• Tape-out ： Submit the file format of the factory after streaming GDSII or GIF. In the R & D stage, the film is streamed —— Multi project chip (multi project
  wafer, MPW); After the chip is finalized, it will be streamed —— Engineering batch .
• EDA Tools ： Pre simulation ：Cadence Analog circuit simulation design environment of the platform ADE(analog design environment);|| Layout check ：Cadence The company's Diva、Dracula, Mentor Graphics The company's Calibre,Synopsys The company's Hercules etc. ;|| LPE：StarRC、Calibre、 Dracula
• DRC: design rule check, Design rule check
• LVS: layout vs schematic, Check the layout and circuit schematic diagram
• LPE: layout parameter extraction, Parasitic parameter extraction