AHB2Standard_ handshake_ Bridge design

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1. Function description

AHB After all, the agreement is with FIFO、RAM When the read-write protocol is different , and AHB yes SoC High speed interface commonly used in system chip , So we need to put AHB The timing of is transformed into the standard handshake timing , Study here AHB Bridge to standard handshake , Implement interface conversion .

Such as below

Yes ,AHB2HANDSHAKE The bridge is used as AHB slave The present , From this we can get the input and output of the bridge

2. Parameters to describe

Group	Signal	Direction	Width(bits)	Description
AHB slave	hrstn	input	1	Reset signal
	hclk	input	1	The clock
	haddr	input	HADDR_WIDTH	Address used to access the internal register
	hburst	input	3	burst Transmission format
	hsize	input	3	Data transfer significand
	htrans	input	2	Transmission status
	hwrite	input	1	1 Said to write ,0 Express reading
	hsel	input	1	Strobe
	hwdata	input	HDATA_WIDTH	Writing data
	hrdata	output	HDATA_WIDTH	Read out data
	hreadyout	output	1	Prepare the sign
	hresp	output	1	Feedback whether there is an error in the current transmission
Standard Handshake	waddr	output	HADDR_WIDTH	Write the address
	wdata	output	HDATA_WIDTH	Writing data
	wr_en	output	1	Write enable
	wready	input	1	Write preparation
	raddr	output	HADDR_WIDTH	Read the address
	rdata	input	HDATA_WIDTH	Reading data
	rdata_val	input	1	Read data effectively
	rd_en	output	1	Reading enable
	rready	input	1	Read preparation

Then the parameter description

Parameter	Units	Description
HADDR_WIDTH	bit	Address bit width
HDATA_WIDTH	bit	write in or Read data bit width
ACCESS_ADDR1、ACCESS_ADDR2、ACCESS_ADDR3、ACCESS_ADDR4	bit	Accessible address

3. logic design

As can be seen from the above figure ,AHB2HANDSHAKE The module serves as AHB slave The emergence of , So from the AHB Slave Design from an angle .

Still follow the idea of state machine . If it is the idea of state machine ,AHB Agreement HTRANS There are four states 、HBURST There are eight states , Which one do we use ？ Or write your own state machine ？

Alternative ideas are based on HTRANS Of IDLE、BUSY、NONSEQ and SEQ Design in four states , After all burst Transfer belongs to NONSEQ or SEQ state .

3.1. HTRANS It doesn't work

Hahaha, I based on HTRANS A half day discovery is designed for the four states of AHB slave There's no way to use a state machine .

Let's take a look at the following waveforms , from AHB Slave Think about it from the perspective of

The picture above shows AHB Compare diaphragmatic areas , The first access to address and data is divided into two beats , Of course, this is also the basis for realizing pipelining . This leads to data transmission in the second beat , The address can change .

So if it takes two beats to access an address , Notice in these two shots address phase And data phase Not in the same HTRANS,data phase Even across multiple HTRANS state .

In other words ,HTRANS This state machine cannot determine hwdata and hrdata Change law of signal .
This is different from the usual state machine design , The usual design idea is that the whole module is divided into several states , Each signal of the module will vary according to different states .
however AHB Agreement HADDR Will be based on HTRANS To determine whether it is valid , and HWDATA and HRDATA The change of does not refer to HTRANS This state .

But as a AHB Slave Don't worry about whether there is a cross HTRANS、HTRANS Whether a state should be delayed , This is AHB Master What to do . As slave, It only needs Write or read the data correctly

So how to treat AHB To the standard handshake timing bridge ？ Or state machine , But we use the most primitive state machine ： read and Write

3.2. IDLE

Of course, nothing is done in this state , When detected AHB master When you want to transfer , namely htrans by NONSEQ when , testing hwrite Judge to transfer to WRITE still READ, Here's the picture

So the state machine is rewritten as

3.3. Write

In this state, write , When the standard handshake sequence is written down, the state ends .

Note the standard handshake timing , So we need to align the address and data in time sequence .

How to achieve it ？ Sequence diagram in IDLE Has shown , As shown in the following figure, with back pressure WRITE

even burst It's OK to write

and WRITE Next state , According to WRITE The last shot htrans Value , The state machine is as follows

About that BUSY Explain .AHB master When entering BUSY The next transmitted control signal will be given , But the control signal will remain the same when the next transmission really comes , So in AHB slave detected wr_en && hready && (htrans == BUSY) Time can still be converted to IDLE state

3.4. read

In this state, read is realized , This state ends when it is determined that the data has been read out .

The same requirement rd_en And rdata Timing alignment , If it is similar to writing , take haddr Beat into raddr, So in data phase The first beat must not read the data , The second shot is the fastest .

in other words , It's bound to backfire , The following figure shows the case with delay .

This state machine is updated to

3.5. Code

module ahb2standard_handshake_bridge#(
	parameter	HADDR_WIDTH = 32,
	parameter	HDATA_WIDTH = 32
	parameter	ACCESS_ADDR1 = 32'h0000_0000_0000_0010,
	parameter	ACCESS_ADDR2 = 32'h0000_0000_0000_0014,
	parameter	ACCESS_ADDR3 = 32'h0000_0000_0000_0018,
	parameter	ACCESS_ADDR4 = 32'h0000_0000_0000_001C
	)(
	input 						hrstn,
	input 						hclk,
	input	[HADDR_WIDTH-1:0]	haddr,
	input	[2:0]				hburst,
	input	[2:0]				hsize,
	input	[1:0]				htrans,
	input						hwrite,
	input						hsel,
	input	[HDATA_WIDTH-1:0]	hwdata,
	output	[HDATA_WIDTH-1:0]	hrdata,
	output						hready,
	output						hresp,
	
	output	[HADDR_WIDTH-1:0]	waddr,
	output	[HDATA_WIDTH-1:0]	wdata,
	output						wr_en,
	input						wready,
	
	output	[HADDR_WIDTH-1:0]	raddr,
	input	[HDATA_WIDTH-1:0]	rdata,
	input						rdata_val,
	output						rd_en,
	input						rready
	);

localparam		IDLE = 2'b00;
localparam		WRITE = 2'b01;
localparam		READ = 2'b11;

reg		[1:0]				cur_state;
reg		[1:0]				nxt_state;
reg		[HADDR_WIDTH-1:0]	waddr_r;
reg		[HADDR_WIDTH-1:0]	raddr_r;
reg							hready_r;
reg							wr_en_r;
reg							rd_en_r;
reg							hresp_r;

[email protected](posedge hclk or negedge hrstn) begin
	if(!hrstn)
		cur_state <= IDLE;
	else
		cur_state <= nxt_state;
end

[email protected](*) begin
	case(cur_state)
		IDLE:
			if(htrans[1]) begin
				if(hwrite)
					nxt_state = WRITE;
				else
					nxt_state = READ;
			end
			else
				nxt_state = IDLE;
		WRITE:
			if(wr_en && hready) begin
				if(!htrans[1])
					nxt_state = IDLE;
				else if(!hwrite)
					nxt_state = READ;
				else
					nxt_state = WRITE;
			end
			else
				nxt_state = WRITE;
		READ:
			if(rdata_val) begin
				if(!htrans[1])
					nxt_state = IDLE;
				else if(hwrite)
					nxt_state = WRITE;
				else
					nxt_state = READ;
			end
			else
				nxt_state = READ;
		default:
			nxt_state = IDLE;
	endcase
end


assign wdata = hwdata[(8 << hsize)-1:0];

[email protected](*) begin
	case(cur_state)
		IDLE:
			hready_r = 1'b0;
		WRITE:
			hready_r = wready;
		READ:
			hready_r = rdata_val;
		default:
			hready_r = 1'b0;
	endcase
end

assign hready = hready_r;

[email protected](posedge hclk or negedge hrstn) begin
	if(!hrstn)
		waddr_r <= 'd0;
	else if(cur_state == IDLE) begin
			if(htrans[1] && hwrite)
				waddr_r <= haddr;
		end
	else if(cur_state == WRITE) begin
			if(wr_en && hready && htrans[1] && hwrite)
				waddr_r <= haddr;
		end
	else if(cur_state == READ) begin
			if(rdata_val && htrans[1] && hwrite)
				waddr_r <= haddr;
		end
end

assign waddr = waddr_r;

[email protected](posedge hclk or negedge hrstn) begin
	if(!hrstn)
		wr_en_r <= 1'b0;
	else if(cur_state == IDLE) begin
			if(htrans[1] && hwrite)
				wr_en_r <= 1'b1;
		end
	else if(cur_state == WRITE) begin
			if(!hready)
				wr_en_r <= wr_en_r;
			else if(htrans[1]) begin
					if(hwrite)
						wr_en_r <= 1'b1;
					else
						wr_en_r <= 1'b0;
				end
			else
				wr_en_r <= 1'b0;
		end
	else if(cur_state == READ) begin
			if(rdata_val && htrans[1] && hwrite)
				wr_en_r <= 1'b1;
		end
end

assign wr_en = wr_en_r;

assign hrdata = rdata[(8 << hsize)-1:0];

[email protected](posedge hclk or negedge hrstn) begin
	if(!hrstn)
		raddr_r <= 'd0;
	else if(cur_state == IDLE) begin
			if(htrans[1] && !hwrite)
				raddr_r <= haddr;
		end
	else if(cur_state == WRITE) begin
			if(wr_en && hready && htrans[1] && !hwrite)
				raddr_r <= haddr;
		end
	else if(cur_state == READ) begin
			if(rdata_val && htrans[1] && !hwrite)
				raddr_r <= haddr;
		end
end

assign raddr = raddr_r;

[email protected](posedge hclk or negedge hrstn) begin
	if(!hrstn)
		rd_en_r <= 1'b0;
	else if(cur_state == IDLE) begin
			if(htrans[1] && !hwrite)
				rd_en_r <= 1'b1;
		end
	else if(cur_state == WRITE) begin
			if(wr_en && hready && htrans[1] && !hwrite)
				rd_en_r <= 1'b1;
		end
	else if(cur_state == READ) begin
			if(!rready)
				rd_en_r <= rd_en_r;
			else if(!rdata_val)
				rd_en_r <= 1'b0;
			else if(htrans[1]) begin
					if(hwrite)
						rd_en_r <= 1'b0;
					else
						rd_en_r <= 1'b1;
				end
			else
				rd_en_r <= 1'b0;
		end
	else 
		rd_en_r <= 1'b0;
end

assign rd_en = rd_en_r;

[email protected](*) begin
	if(cur_state == WRITE && wr_en && hready) begin
		if(waddr != ACCESS_ADDR1 
			&& waddr != ACCESS_ADDR2
			&& waddr != ACCESS_ADDR3
			&& waddr != ACCESS_ADDR4)
			hresp_r = 1'b1;
		end
	else if(cur_state == READ && rdata_val) begin
			if(raddr != ACCESS_ADDR1 
				&& raddr != ACCESS_ADDR2
				&& raddr != ACCESS_ADDR3
				&& raddr != ACCESS_ADDR4)
				hresp_r = 1'b1;
		end
	else
		hresp_r = 1'b0;
end

assign hresp = hresp_r;

endmodule