I2C read / write process

I2C Data communication consists of data lines (SDA) And a clock line (SCL) form First pair I2C initialization ： Main mode 、 Interrupt vector IRQ interrupt 、 Bus rate Data reading and writing process ：
1、 The main equipment sends a start signal (Start)
Start signal (Start)： Clock line (SCL) During high level , cable (SDA) From high to low , It is a start signal .
2、 The main device sends out 1 Bytes of slave address information
The lowest bit is the read / write control code (0 For writing ,1 For reading ), high 7 Bit is the slave address code .
Such as AT24C256 Address ：

3、 Send an approval signal from the device
Answer signal (Ack)： That is, the approval signal , There are two cases ：
(a)、 The master device writes to the slave device , Every time you write correctly 1 Bytes of data , The slave device will connect the data line in the next clock cycle (SDA) Pull it down , It is a reply signal .
(b)、 The master device reads the slave device , After each correct reading 1 Bytes of data , The master device will connect the data line in the next clock cycle (SDA) Pull it down , It is a reply signal . notes ： When reading from a slave device , The master device does not send a response signal after the last byte of data is received , Instead, it sends an end signal directly .
4、 The master device starts reading and writing to the slave device
If it is Read operations , Then every read 1 byte , The master device will send a reply signal (Ack) To the slave device , If it is Write operations , Then every time 1 byte , The slave device will send a reply signal (Ack) To main equipment .
5、 The main equipment sends an end signal (Stop)    
Clock line (SCL) During high level , cable (SDA) From low to high , It is an end signal . in other words ,I2C The bus is in the communication process , All data read and write operations must be on the clock line (SCL) For low level , And on the clock line (SCL) Data lines must be maintained for high power levels (SDA) Signal stability , Anything that happens on the clock line (SCL) Data line during high level (SDA) All level changes on the are considered as start or end signals .